Verilog RTL Programming Practice

"Verilog RTL Programming Practice" is an engineering practice course developed with reference to the training materials "Digital VLSI Design with Verilog" and "Verilog Digital VLSI Design Tutorial" (Chinese translation) of the Silicon Valley Institute of Technology in the United States. The course is not only a theoretical description of the semantics and syntax of the Verilog language, but more importantly, it summarizes and sublimates the Verilog RTL programming technology from the perspective of the use of logic simulation tools and logic synthesis tools. It also covers important Verilog programming knowledge and skills, especially the construction of test platforms.

• Chapter 1：Verilog RTL Programming Practice 1 (1 hours and 21 minutes and 11 seconds)

• Chapter 2：Verilog RTL Programming Practice 2 1 (15 minutes and 54 seconds)

• Chapter 3：Verilog RTL Programming Practice 2 2 (47 minutes and 42 seconds)

• Chapter 4：Verilog RTL Programming Practice 3 (1 hours and 17 minutes and 51 seconds)

• Chapter 5：Verilog RTL Programming Practice 4 (1 hours and 13 minutes and 55 seconds)

• Chapter 6：Verilog RTL Programming Practice 5 (1 hours and 19 minutes and 18 seconds)

• Chapter 7：Verilog RTL Programming Practice 6 (1 hours and 43 minutes and 46 seconds)

• Chapter 8：Verilog RTL Programming Practice 7 1 (5 minutes and 11 seconds)

• Chapter 9：Verilog RTL Programming Practice 7 2 (32 minutes and 35 seconds)

• Chapter 10：Verilog RTL Programming Practice 8 (1 hours and 14 minutes and 41 seconds)

• Chapter 11：Verilog RTL Programming Practice 9 (49 minutes and 18 seconds)

• Chapter 12：Verilog RTL Programming Practice 10 (1 hours and 25 minutes and 21 seconds)

• Chapter 13：Verilog RTL Programming Practice 11 (1 hours and 29 minutes and 43 seconds)

• Chapter 14：Verilog RTL Programming Practice 12 (49 minutes and 48 seconds)

• Chapter 15：Verilog RTL Programming Practice 13 (1 hours and 16 minutes and 4 seconds)

• Chapter 16：Verilog RTL Programming Practice 14 (1 hours and 19 minutes and 20 seconds)

• Chapter 17：Verilog RTL Programming Practice 15 (56 minutes and 37 seconds)

• Chapter 18：Verilog RTL Programming Practice 16 (59 minutes and 7 seconds)

• Chapter 19：Verilog RTL Programming Practice 17 (51 minutes and 18 seconds)