Pan Wenming's series of tutorials on simple design methods and efficient verilog design templates

Using multiple templates helps us save time. Ming Deyang's template includes counters, state machines, FIFOs and module structures of the minimalist design method, which are the most common parts of RTL code. When using these templates, engineers only need to fill in the blanks in order to quickly design, saving a lot of time.

• Chapter 1：01 GVIM tutorial based on Ming Deyang’s course (27 minutes and 49 seconds)

• Chapter 2：02 Use GVIM to create templates (6 minutes and 59 seconds)