Switcher adds programmable PWM duty cycle clamp

Power supply applications require the use of a duty cycle clamp. Such applications include those using current sensing transformers and two-switch forward converters. Without a duty cycle clamp, the transformer may saturate, causing catastrophic failure of the system. However, to reduce design costs, many power supply designers use less expensive 8-pin PWM controllers without a duty cycle clamp. This design idea shows how to add a less expensive duty cycle clamp to a PWM controller.

You can add this clamp circuit to most PWM controllers to provide a programmable duty cycle clamp (see Figure 1). This circuit consists of a few passive components, a hysteresis comparator, and a gate drive IC. Resistor R1 and capacitor C1 program the dead time of the duty cycle clamp. Resistor R2 and diode D1 reset the timing circuit when the PWM controller output goes low. Resistors R3, R4, and R5 set the voltage node of the comparator, VTRIP, to 5V. Resistor R5 adds a -2.5V hysteresis voltage to the comparator to ensure circuit stability.

The following example shows how to set up the circuit in Figure 1 to obtain a maximum duty cycle Dmax of 0.9. The PWM controller operates at a switching frequency fs, which is

100kHz. Most PWM controllers cannot achieve 100% duty cycle and have a specific dead time. In this case, the dead time is 300nsec. Setting the timing capacitor also requires knowing the maximum PWM output voltage, VOUT. In this case, the maximum output voltage is 12V. The timing capacitor is approximately 130pF. The design uses a standard 120pF capacitor. The following equation details the calculation steps: t = (1-DMAX)(1/fS)-dead time = 700 nsec, and

A SPICE simulation was performed on the circuit in Figure 1 to ensure that the duty cycle clamping function worked properly in the circuit. Figure 2 shows the results of this simulation. VOUT is the output of the PWM controller, VT is the voltage at the inverting pin of the comparator, VTRIP is the voltage at the non-inverting input of the comparator, and Gate is the output of the gate driver IC. From the waveforms in Figure 2 you can see that the duty cycle clamping works correctly, achieving 90% clamping of the gate driver output.