Space target collision warning system based on FPGA

Abstract: In order to solve the problem of collision between space targets and spacecraft, a target collision warning system based on FPGA is designed, which uses the three-dimensional coordinates of the on-orbit target as the data to be processed for fast parallel processing. The system is based on the content addressable memory (CAM) IP core and MicroBlaze soft core controller in the Xilinx FPGA chip, and is built using the embedded development kit (EDK); and the screening algorithm for space dangerous targets is designed, and the software and hardware codes are written and loaded into the above system for actual operation verification. The verification results show that the system realizes the function of fast screening of dangerous targets among 16 targets. By using the ChipScope logic analysis tool for waveform analysis, it can be seen that the time required for the system to perform a screening operation is 1.8 s.
Keywords: field programmable gate array; Microblaze; content addressable memory; space target; collision

With the continuous development of human space activities, the spatial density of space debris has posed a threat to the safety of spacecraft, especially in the low-Earth orbit, where the density of debris is even greater and its number is still increasing rapidly. Spacecraft are often hit by space debris. The number of targets on orbit in space is increasing, and the amount of calculation required for collision warning of space targets is also increasing rapidly. Given the high speed of parallel computing, it is suitable to apply parallel computing to screen dangerous targets and then perform warning operations. The use of CAM (content addressable memory) and MicroBlaze soft-core controller in FPGA can achieve fast parallel screening of dangerous targets.

1 CAM
1.1 CAM Overview
CAM is a special memory that stores data items in an array. The number of bits of each data item is called word width, and the number of all data items in CAM is called CAM depth. Word width and depth can characterize the capacity of CAM.
CAM is based on content addressing and achieves fast matching through hardware circuits. The parallel processing characteristics of CAM make it very popular in the field of data sorting, and it is widely used in Ethernet URL search, data compression, pattern recognition, high-speed caching, high-speed data processing, data security and data encryption.
1.2 CAM Working Principle
The two most basic ports of CAM are data line and address line. The data line is used as an input port to store data that needs to be processed by CAM, and the address line is used as an output port to output the processing result of CAM - the address where the matching data is located. Figure 1 shows a CAM with a depth of 4 and a word width of 4. If the binary number 1100 is placed on the data line, the output matching result will be 0011. As shown in Figure 1, each binary number in the result corresponds to each data inside the CAM. If the data on the data line is equal to the data inside the CAM, the corresponding bit output is 1, and if they are not equal, the output is 0. Since the CAM has a parallel matching feature, it is very suitable for simultaneous parallel matching of multiple targets in space.

2 MicroBlaze Soft-Core Controller
MicroBlaze is a microprocessor IP core based on Xilinx FPGA. It can complete the design of programmable system-on-chip (SOPC) together with other peripheral IP cores. MicroBlaze processor adopts RISC architecture and Harvard structure 32-bit instruction and data bus, and has 32 32-bit general registers inside; its internal structure is shown in Figure 2.

Using the EDK (Embedded System Development Kit) provided by Xilinx, the design of the embedded processor system can be easily completed under the parameterized graphical interface. Its outstanding advantages are: first, design flexibility; second, the ability to integrate user-defined IP cores, so that the algorithm can be executed in parallel in hardware rather than serially in software, thereby greatly accelerating the execution speed of the software.

3 Algorithm Design
3.1 Algorithm Analysis
The collision warning of space targets can actually be transformed into finding targets with collision danger by judging and comparing the distances between targets. Since the position of space targets can be represented by three-dimensional spatial coordinates, the judgment of the distance between any two targets can be further transformed into the comparison of their coordinates.
3.2 Algorithm Description
Assume that only three targets need to be matched with coordinates, and their coordinates are A (xA, yA, zA), B (xB, yB, zB), and C (xC, yC, zC). A CAM with a depth of 3 is required. First, the z coordinate is processed and the x coordinates of the three targets are stored in the CAM, as shown in Figure 3.

Then, xA, xB, and zC are placed on the data line for matching operations. After three matching operations, three matching results RxA, RxB, and RxC are obtained. The same operation is performed on the y and z coordinates, and the matching results of y and z are RyA, RyB, RyC and RzA, RzB, and RzC, respectively. The results are all 3-bit binary numbers. Then, the internal coordinates of each target are compared. For example, by comparing the three matching results RxA, RyA, and RzA of target A, it can be known whether there are items with the same three coordinates as target A. For example, if RxA, RyA, and RzA are 101, 101, and 101 respectively, it means that the coordinates of target A and target C are matched, and then it can be judged that there is a possibility of collision between target A and target C.
Different from conventional memory and software matching methods, CAM performs data matching operations in parallel, which can greatly improve the data matching speed and thus improve system efficiency.

4 Hardware platform construction and operation
4.1 CAM module implementation
Using the IP core resources provided by Xilinx, by configuring the CAM IP core parameterization graphical interface, as shown in Figure 4, a CAM module with a depth of 16 and a word width of 32 is instantiated inside the FPGA. Its basic parameters are shown in Table 1.

As shown in Table 1, by selecting the memory type as Block Memory, a CAM module based on the FPGA's on-chip BRAM can be instantiated. Compared with the CAM based on SRL16 (16-bit shift register lookup table), its write cycle only requires 2 clock cycles, and the time required for the write operation is 1/8 of the latter, which improves the system speed.

There are three options for output address encoding: Multi Match Unencoded, Single Match Unencoded, and Binary Encoded. The first encoding method can output all possible matches from the address line, while the latter two encoding methods can only output one match on the address line.
After actual verification, the synthesis report obtained by the ISE synthesis tool XST shows that the resources occupied by a CAM with a depth of 16 and a word width of 32 in the FPGA chip model XC3S700AN ​​are shown in Table 2.

It can be seen from Table 2 that block RAM accounts for a large proportion of the resources occupied by a CAM with a depth of 16 and a word width of 32. This is because the CAM module implemented inside the FPGA is based on the block RAM resources of the FPGA, so it consumes more block RAM resources. Therefore, when selecting FPGA chips in actual applications, chips with rich block RAM resources should be selected.

4.2 Connection between MicroBlaze soft-core controller and CAM
A MicroBlaze soft-core controller is configured in the FPGA chip to implement a series of controls on the CAM, such as reset, write data, read data, etc. MicroBlaze is connected to the CAM through the PLB bus. At the same time, for the convenience of debugging, peripheral modules such as serial ports are connected to the PLB bus. The system module diagram is shown in Figure 5.

4.3 System Execution
During the system execution, Microblaze, as a controller, controls the CAM by executing the software program written in C language. Its specific operation process is shown in Figure 6.

Inside the system, the implementation and download of the entire project is divided into four steps: first, generate the hardware netlist of the system, that is, synthesize the embedded system; second, generate the bitstream file of the system hardware architecture; compile the software again, and combine the bitstream generated by the software code and the bitstream of the system hardware into one to form a complete system description bitstream; finally, download the complete bitstream to the FPGA chip.
4.4 Verification result analysis
After analyzing the processing results, it can be seen that this system verifies the correctness of the design algorithm. The clock frequency of the built system is 62.5 MHz, and the clock cycle is 16 ns. By adding a clock counter inside the code and using the ChipScope logic analyzer for waveform analysis, it can be seen that the number of clock cycles required for the system to perform a screening operation is 114 296 649, which is about 1.8 s.
4.5 System expansion capability analysis
In subsequent research, the number of targets to be screened can be increased by expanding the CAM capacity. The expansion of CAM capacity requires more FPGA chip resources, and its operating frequency will be reduced. Taking a Spartan3A chip as an example, the relationship between the three is shown in Table 3, Table 4, and Table 5.

Considering the cost issue, the chip used in this design is the XC3S700AN ​​from Xilinx. As shown in Tables 3 to 5, when expanding the CAM capacity, it is necessary to comprehensively consider the relationship between the required CAM capacity, the selected FPGA chip resources, and the operating frequency.

5 Conclusions
The target collision warning platform built with Xilinx's MicroBlaze soft-core controller and content addressable memory (CAM) realizes the screening operation of dangerous targets in a target group with a total number of 16 targets. The soft-core controller and the CAM module are implemented in the same FPGA chip, which is convenient to manage and operate, and facilitates the miniaturization and integration of the system. Limited by the capacity of the FPGA itself, when expanding the CAM capacity, it is possible to consider using a larger capacity FPGA chip, or using an external large-capacity proprietary CAM chip to achieve parallel matching operations of large-scale targets.