Introduction to FPGA Basics (Part 2)

Many of you are familiar with JTAG downloading under CPLD, but when it comes to FPGA, you are more or less confused. How come
the configuration chip appears? Why do you need different download cables and different download modes? I will talk about my personal opinions based on what I know
and send you some information. I hope that friends passing by will give me some praise and the moderator will give me some prestige. If you have any questions
, please discuss them together. You are welcome to criticize me.

1. FPGA devices have three types of configuration download methods: active configuration method (AS), passive configuration method (PS) and the most commonly used
(JTAG) configuration method.

AS is guided by the FPGA device to configure the operation process, which controls the external memory and initialization process. The EPCS series, such as EPC
S1, EPCS4 configuration devices, are dedicated to AS mode and currently only support the Cyclone series. Use Altera serial configuration devices to
complete. Cyclone is in an active position and in a slave position during configuration. Configuration data is sent
to FPGA through the DATA0 pin. Configuration data is synchronized on the DCLK input, and 1 bit of data is transmitted in 1 clock cycle. (See attached figure)

The PS configuration process is controlled by an external computer or controller. This is done through enhanced configuration devices (EPC16, EPC8, EPC4) and other configuration devices. During PS configuration, the configuration data is sent from the external storage component to FPG
A through the DATA0 pin. The configuration data is latched on the rising edge of DCLK, and 1 bit of data is transmitted in 1 clock cycle. (See attached figure)

The JTAG interface is an industry standard, mainly used for chip testing and other functions, using the IEEE Std 1149.1 Joint Boundary Scan
interface pins, supporting the JAM STAPL standard, and can be completed using the Altera download cable or host controller.

When the FPGA is working normally, its configuration data is stored in SRAM and must be downloaded again when the power is turned on. In experimental systems,
debugging is usually performed using a computer or controller, so PS can be used. In practical systems, in most cases,
the FPGA must actively guide the configuration operation process. At this time, the FPGA will actively obtain the configuration data from the peripheral dedicated storage chip, and
the FPGA configuration information in this chip is burned into the designed pof format file using an ordinary programmer.

Dedicated configuration device: EPC type memory

Commonly used configuration devices: epc2, epc1, epc4, epc8, epc1441 (now seems to have been gradually eliminated) etc.

For cyclone and cycloneII series devices, ALTERA also provides configuration devices for AS mode, EPCS series. For example,
EPCS1 and EPCS4 configuration devices are also serially configured. Note that they are only applicable to cyclone series.

In addition to single-bit configurations such as AS and PS, some devices now support parallel configurations such as PPS and FPS, which improves
the configuration speed. Of course, the external circuit is also somewhat different from PS. There are also processor configurations such as JRUNNE
R, etc. If you need it, search on Baidu. There are at least ten types. For example, Altera's configuration methods mainly include Passive
Serial (PS), Active Serial (AS), Fast Passive Parallel (FPP), Passive Parallel
Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial Asynchronous
(PSA), JTAG and other seven configuration methods. Among them, Cyclone supports three configuration methods: PS, AS, and JTAG.

2 For the configuration of FPGA chip, AS mode can be used. If EPCS chip is used and
programmed through a download line, then the initial 'nCONFIG, nSTATUS' should be pulled up. If multiple configuration modes are considered,
jumper design can be used. The configuration mode can be switched in the jumper. The pull-up resistor value can be 10K

3. Tip in PS mode: If you use a cable to configure the FPGA chip on the board, and the FPGA chip already has a configuration chip
on the board, then you must isolate the cable and the signal of the configuration chip. (See the figure below). Generally, the configuration
chip is not soldered during normal debugging. At this time, the cable is used to download the program. Only after the debugging is completed, the program is burned into the configuration chip, and then
the chip is soldered. Or the configuration chip can be easily removed and soldered. In this way, it can be easily
debugged if there is a problem.

Tips in AS mode: I have used AS download on a board. The configuration chip has always been soldered on the board. The original AS mode
will automatically disable the configuration of the FPGA when downloading the configuration chip with a cable, while the PS mode requires circuit
isolation.

4. Generally, jtag is used to configure epc2 and flex10k, and then epc2 is configured with ps to configure flex10k. This is better. (
This is what I saw on the Internet. Can it be used this way? I doubt it.) I hope someone can tell me.

5. Download cable. Altera's download cables include ByteBlaster, ByteBlasterMV, and ByteBlaster
II. Now they also have USB-blaster. Since BB is rarely used and USB-Blaster is
too expensive, here we will talk about the difference between BBII and BBMV.

BBII supports multi-voltage power supply 5.5v, 3.3v, 2.5v, 1.8v;

BBII supports three download modes: AS, which can program Altera's AS serial configuration chip (EPCS series)

PS, can configure FPGA

JTAG, can program FPGA, CPLD, Altera configuration chip (EPC series)

BBMV only supports PS and JTAG

6. Generally, when making FPGA experimental boards (such as the cyclone series), the AS+JTAG method is used. In this way, the JTAG method can be used for debugging
. Finally, after the program has been debugged correctly, the AS mode is used to burn the program into the configuration chip. In addition, this has an
obvious advantage. When the AS mode cannot be downloaded, the Quartus built-in tool can be used to generate
a jic file that can be used in the JTAG mode to verify whether the configuration chip is damaged. The method is shown in the attachment (this is written by Junlong people and
is excerpted from our forum. If there are any copyright issues, please forgive me).

7. Altera's FPGA can be configured through microcontrollers, CPLDs, etc. The main principle is to meet the timing in the datasheet
. I won't go into details here. Interested friends can read the following articles and should be able to understand what's going on
.

8. During configuration, Quartus software operation part:

(1).assignment-->device-->device&pin options-->select configuration scheme, conf
iguaration mode, configuration device, note

The configuration mode is not selectable in machines that do not support remote and local updates, and the configuration device
will generate a pof file based on different configuration chips.

If you select Automatic, the device with the smallest density and the one that fits your design will be selected.

(2) You can define the role of the dual-port pins after configuration. In the device & pin option --> dual-purpose
pins -->, you can continue to use them as I/O ports after configuration.

use

(3) There are also many options that can be checked under the general menu. By default, no changes are usually made. For specific usage, see alter
a configuration

handbook, volume 2, section II.

(4) Scope of application of files with different suffixes:

sof (SRAM Object File) is used when the configuration data is directly downloaded to the FPGA in PS mode.
It is applicable to USB BLASTER, MA STERBLASER, BBII, and BBMV. QuartusII will automatically

All other configuration files are generated by sof.

pof (Programmer Object File) is also automatically generated by quartusII, applicable to BBII, and downloads configuration
data to the configuration chip in AS mode

rbf (Raw Binary File) is a binary file for microprocessors. It is useful in PS, FPP, PPS, and PPA configurations.

rpd (Raw Programing Data File) contains a binary file of the bitstream, which can be configured in AS mode and can only
be generated from a pof file

I won't say much about hex (hexadecimal file), there are many in the microcontroller

ttf (Tabular Text File) is suitable for FPP, PPS, PPA, and bit-wide PS configuration methods

sbf (Serial Bitstream File) uses PS mode to configure Flex 10k and Flex6000

Jam (Jam File) is specifically used for program, verigi, blank-check

I have reviewed the information on Altera's FPGA download configuration in the past few days, and now I summarize my learning experience as follows:

1. Depending on the role of the FPGA in the configuration circuit, the configuration data can be loaded into the target device in three ways:

(1) FPGA active mode: FPGA actively outputs control and synchronization signals to the FPGA serial configuration chip (EPCS series). After receiving the command, the configuration chip sends the configuration data to the FPGA to complete the configuration process. In AS mode, FPGA must be used in conjunction with the AS serial configuration chip. Its interface with FPGA is four signal lines, namely: serial clock input (DCLK), AS control signal input (ASDI), chip select signal (nCS), and serial data output (DATA).

(2) FPGA passive mode: In passive mode, the configuration process is initiated and controlled by other devices in the system. These devices can be configuration chips (EPC series), or single-board microprocessors, CPLDs, etc. FPGA is completely passive during the configuration process and only outputs some status signals to cooperate with the configuration process; in PS mode, four signals are required to complete the configuration process: configuration clock (DCLK), configuration data (DATA0), configuration command (nCONFIG), status signal (nSTATUS), and configuration completion indication (CONF_DONE).

(3) JTAG mode: JTAG configuration can be performed using Altera's download cable, or by simulating JTAG timing through an intelligent host. The JTAG interface consists of four required signals: TDI, TDO, TMS, and TCK, and an optional TRST.

2. If you use the ByteBlasterII download cable, the following three configuration methods are supported:

AS mode: Program the AS configuration chip (ECPS series);

PS mode: FPGA can be configured;

JTAG method: can program FPGA, CPLD and Altera configuration chip (EPC series).

3. Notes on AS and PS modes

PS mode: If you use a cable to configure the FPGA chip on the board, and this FPGA chip already has a configuration chip on the board, then you must isolate the signal between the cable and the configuration chip. Usually, the configuration chip is not soldered during normal debugging. At this time, use the cable to download the program. Only after the debugging is completed, the program is burned into the configuration chip, and then the chip is soldered. Or the configuration chip can be easily removed and soldered. In this way, it can be easily debugged if there is a problem.

In AS mode: I have used AS download on a board, and the configuration chip has always been soldered on the board. The original AS mode will automatically prohibit the configuration of the FPGA when downloading the configuration chip using a cable, while the PS mode requires circuit isolation.

4. Generally, when making FPGA experimental boards (such as the cyclone series), the AS+JTAG method is used, so that the JTAG method can be used for debugging. Finally, after the program has been debugged correctly, the AS mode is used to burn the program into the configuration chip. This has an obvious advantage, that is, when the AS mode cannot be downloaded, the Quartus built-in tool can be used to generate a jic file that can be used in the JTAG mode to verify whether the configuration chip is damaged.