Design of video decoding system based on ADV7183B

Abstract: MSP430F169 is used to control the video decoding chip ADV7183B to process the composite video, S-Video and color difference component video input sources, thereby outputting 8 bit/16 bit CCIR656 YCrCb type 4:2:2 digital video data, which is then further processed by format conversion, filtering, etc. and displayed through the DVI interface.

Human visual information accounts for more than 70% of all information received. With the advancement of modern science and technology and social development, the amount of information people are exposed to is also increasing. Therefore, the importance of display technology is increasing. Video technology [1] has also experienced a development from analog video to digital video, and its application in people's daily life is becoming more and more extensive, such as video conferencing, high-definition digital television (HDTV), mobile video and 3G visual communication.

At present, there are many types of digital imaging equipment, and the audio and video processing hardware and software technologies are highly developed [2], which has contributed to the popularity of digital video. For a long time, image processing will become a frontier field and a hot topic in information technology. The application of image processing technology has achieved good social and economic benefits. The main reason is that the development and maturity of computer technology and large-scale integrated circuit technology have made the use of embedded systems as video image input and output processing gradually become the mainstream. Hardware solutions have also developed from dedicated processing chips and DSP to FPGA, greatly improving the flexibility and miniaturization of the system.

1 System Design

By configuring the single-chip microcomputer MSP430F169 and the decoding chip ADV7183B, the entire video decoding system can be flexibly configured according to the input video source to output different digital video data. The maximum computing speed of MSP430F169 reaches 8 MIPS, and it has the characteristics of easy operation and low power consumption [3-4]. In particular, it can transmit data with the decoder through the I2C interface to realize the decoding of video input sources of different formats. The ADV7183B is a comprehensive video decoding chip [5-6]. It can automatically convert an analog video baseband signal compatible with the international standard NTSC or PAL into another YCrCb type 4:2:2 digital video data compatible with 8 bit/16 bit CCIR656. Its flexible digital output interface can complete the video decoding and conversion functions in a system based on a buffer structure and a line lock clock. The hardware block diagram of the video decoding system is shown in Figure 1. MSP430F169 is the main control chip. For different analog video sources, C language programming is used to configure the registers of the decoding chip ADV7183B accordingly to generate digital video data and line and field signals that meet the requirements, so as to facilitate filtering and display by the video post-processing system.

Digital video data is obtained by decoding the analog video signal into Y, U, and V components, and then performing A/D quantization sampling on them respectively, converting them into digital video streams, and outputting them in the above order in time. Here, the CCIR656 (Consultative Committee of International Radio) standard established in 1927 [7-8], also known as ITU-R BT.656, is used. This standard stipulates that the sampling frequencies of the three components Y, U, and V are 13.5 MHz, 6.75 MHz, and 6.75 MHz respectively. Linear quantization is used, and the quantization bit of each sample point is 10 bits for the studio and 8 bits for transmission. The ratio between the three component samples of Y, U, and V is 4:2:2, and the data format is shown in Figure 2.

In Figure 2, T is the sampling clock 37 ns (27 MHz); SAV is the timing reference mark code for the start of effective video; EAV is the timing reference mark code for the end of effective video; each reference signal consists of 4 cycles of data, the format is FF, 00, 00, XY, expressed in hexadecimal, the first 3 are fixed prefixes, and the fourth word is used to define the odd and even fields, field blanking and line blanking information. During the blanking period, 80 H, 10 H, 80 H, 10 H are transmitted; during the effective period, Cb, Y, Cr, Y, Cb, Y are transmitted in sequence. [page]

2 ADV7183B Setup

According to actual needs, the Analog Devices ADV7183B chip is used as the system decoding chip. It is a comprehensive video decoding chip that can process input video sources in three formats: CVBS, S-Video, and YPrPb under the NTSC or PAL standard. It is widely used in electronic products such as projectors, digital TVs, DVDs, and game consoles. The main features of ADV7183B [9] are as follows:

(1) With internal line-locked system clock (LLC) and adaptive digital line length tracking (ADLLT) circuit, it can provide dual video locking function;

(2) It has a real-time clock, information output function, and a 3-line chroma comb filter;

(3) Complete AGC and clamp control functions, allowing programmable video adjustments for chroma, brightness, saturation and contrast;

(4) Automatic NTSC or PAL detection and 12 analog video input channels;

(5) Can be set to two-wire continuous bidirectional port mode and is compatible with I2C;

(6) Support different modes of video input and 16-bit width bus digital output;

(7) The peak-to-peak value of the input is 0.5 V to 2 V.

Through different configurations, the 6 analog video input channels of ADV7183B can support 6 CVBS input signals, 3 S-video input signals and 2 YPrPb analog video input signals. The type and channel of the input source can be controlled by register INSEL. In addition, ADV7183B supports 3 output interface modes: LLC-compatible synchronous pixel interface, CAPI interface and SCAPI interface. The default mode is LLC-compatible 8-bit CCIR656 data.

When designing the circuit, the working crystal of ADV7183B is 27 MHz, and ALSB is the address chip select port. Due to the design requirements of the software program, it is grounded and set to a low level. CVBS is connected to the AIN5 pin, S-Video is connected to the AIN1 and AIN4 pins, and YPrPb is connected to the AIN2, AIN3 and AIN6 pins; P0~P15 are data output terminals; LLC1 and LLC2 are clock output ports. When the data output is 8 bit, LLC1 is 27 MHz and LLC2 is 13.5 MHz. When the data output is 16 bit, LLC1 and LLC2 are both 13.5 MHz; HS is the horizontal synchronization signal output, VS is the field synchronization signal output, and FIELD is the odd and even field signal output. When the system is powered on, the two LED lights on the board will flash 10 times alternately, prompting the user to select the input source channel by pressing the button: SW1 button selects S-Video video source input, SW2 button selects YPrPb video source input, if no operation is performed, the default CVBS video source input is used.

Since both MSP430F169 and ADV7183B have their own I2C modules, the system uses the I2C bus protocol to configure various registers of the decoding chip through an interrupt program to generate YCrCb type 4:2:2 digital video data. The software flow chart is shown in Figure 3.

First, initialize the clock and transmission mode to make the MSP430F169 work in the required mode; second, initialize the I2C function to prepare to send the slave address to the I2C bus and wait for the slave on the bus to respond. If there is no response, repeat the transmission. If there is a response, initialize the communication and open the interrupt to send the register address and data required for configuration [10-11]. It should be noted that the host mode and transmission mode settings must be initialized before each data transmission, because these two flags will be automatically cleared after each data transmission. [page]

In order to make the ADV7183B work properly, the configuration contents of several main registers are as follows:

(1) Input selection register INSEL, address 0x00. According to the external interface, the user can select the input channel and input mode of the analog video source by setting this register, that is, select CVBS, S-Video or YPrPb input. In this system, the CVBS signal is input through AIN5, so the register content is set to 0x04; the Y of the S-Video signal is connected to AIN1, and C is connected to AIN4, so the register content is set to 0x06; the Y of the YPrPb signal is connected to AIN2, Pb is connected to AIN3, and Pr is connected to AIN6, so the register content is set to 0x0A. At the same time, the other unconnected input channel pins must be grounded.

(2) Output mode selection register OF_SEL, address 0x03. By setting this register, the user can control the output data to be 8 bit or 16 bit. However, this register must be set together with the pixel clock register (LLC_PAD_SEL, address 0x8F). When outputting 16 bit data, the pixel clock is 13.5 MHz; when outputting 8 bit data, the pixel clock is 27 MHz (default setting). So in the program, when outputting 8 bit, 0x03 is set to 0x0C, 0x8F is set to 0x00; when outputting 16 bit, 0x03 is set to 0x00, 0x8F is set to 0x50.

(3) ADC low power control register, address 0x3A. This register can select the number of ADCs to work. In CVBS mode, ADC1 and ADC2 are low power, that is, they do not work; in S-Video mode, ADC2 is low power; and in YPbPr mode, all three ADCs work. At the same time, the corresponding register addresses 0xC3 and 0xC4 need to be configured. These two registers set the pins to which the three ADCs are connected. According to the external analog input source, in CVBS mode, ADC0 is connected to AIN5, then 0xC3 is set to 0x05, and 0xC4 is set to 0x80; in S-Video mode, ADC0 is connected to AIN1, ADC1 is connected to AIN4, then 0xC3 is set to 0x41, and 0xC4 is set to 0x80; in YPrPb mode, ADC0 is connected to AIN2, ADC1 is connected to AIN3, and ADC2 is connected to AIN6, then 0xC3 is set to 0x32, and 0xC4 is set to 0x86.

(4) For the registers related to the horizontal and vertical synchronization signals, the default settings can generally be used.

3 Experimental Results

During system debugging, a color digital camera was used as the video input source, that is, the analog video signal in CVBS format was input, and the waveform of the output pin was captured by a logic analyzer to observe the corresponding signal and output data. By constantly modifying the program, the acquisition and display of video images were finally realized. Figure 4 is the waveform of the output mode selection register of ADV7183B set by MSP430F169. It can be seen that the timing meets the transmission timing of the standard I2C bus protocol: start-slave device address (0x40)-response-slave device register address (0x03)-response-write data (0x0C)-response-end. Figures 5 and 6 are the decoded video data. In Figure 5, according to the fixed prefix FF 00 00 F1, it can be seen that the information contained in F1 (1111 0001) indicates that the line jumps from 0 to 1 and the field jumps from 0 to 1. The transmission data enters the blanking period of the line and field. In Figure 6, from the fixed prefix FF 00 00 80, we can see that the information contained in 80 (1000 0000) indicates that the line jumps from 1 to 0, and the field jumps from 1 to 0, and the transmission data enters the valid period of the line and field. This shows that the video data output by the video decoding system complies with the CCIR656 standard and meets the design requirements.

In summary, this video decoding system uses MSP430F169 to set up the decoding chip ADV7183B, which has the characteristics of low power consumption, compactness and flexibility. At the same time, as a video input front end, it converts the analog video source of the color camera into 16-bit YCrCb type 4:2:2 digital video data, and after format conversion, filtering and other processing, it is clearly displayed on the CRT through the DVI interface, meeting the design requirements and being able to provide good digital video data for the corresponding video post-processing equipment (such as DSP, FPGA, etc.). [page]

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