Video signal processing in DVB_C set-top box

    Abstract: Set-top box is one of the key technologies of interactive TV. The video signal processing technology in DVB_C STB is introduced from aspects such as MPEG 2 demultiplexing, video encoding and decoding, video output, and video and audio synchronization.

    Keywords: digital set-top box, synchronization, interactive television (ITV)

    With the rapid development of information technology, communication technology, computer technology, and television technology have entered a new era of mutual integration. The emerging interactive television (ITV) is the concrete embodiment of this combination. The so-called interactive TV is a kind of TV controlled by the audience. The audience can make choices and decisions between and within the program. It is a new type of TV technology in the form of asymmetric duplex. Digital set-top box is one of the key technologies. As the user terminal in the ITV system, it is the bridge between ordinary TV and broadband transmission network. Through STB, users can watch high-definition (such as MPEG 2 standard) images on ordinary TV sets; and they can enjoy a series of attractive services such as video on demand and home shopping without leaving home.

    What the author designed is a set-top box for cable TV. Its main function is to convert digital TV signals into analog TV signals, so that during the transition period from analog TV to digital TV, the analog TV can receive digital TV programs; and on this basis Video on demand, FireWire interface (IEEE 1394) and other functions have been added. The internal structure of the set-top box is mainly divided into two parts: video signal processing and audio signal processing. Among them, video signal processing includes two parts: (1) demultiplexing, decoding and format conversion processing of the video signal itself; (2) synchronization of video signals and audio signals.

1 System structure

    Figure 1 is the functional module block diagram of the set-top box designed by the author.

    The system uses VLSI's development platform: VES2761 evaluation board and JumpStart ARM 3.3a development software.

    The front-end part receives the signal output from the cable TV cable, performs frequency conversion, QAM decoding, deinterleaving, decoding RS code, descrambling, etc., and then outputs the standard code stream before MPEG 2 demultiplexing, that is, the transmission code stream. This part is mainly completed by a VES1820 chip.

    The demultiplexing and central processing unit (main control CPU) are integrated on one chip VES2700. The MPEG 2 transport code stream is demultiplexed into three parts: system stream, video stream and audio stream. VES2700 also provides IEEE 1394, IEEE 1284, RS232, Modem, I2C, smart card and infrared communication interfaces.

    The chip VES6100 requires an external SDRAM (at least 2MB), so it can work as an MPEG 2 (MP@ML or MP@SL) decoding system and output the decoded data stream into audio signals and video signals. The audio signal is then decoded and amplified by PCM and can be directly used as the input signal of the speaker. The signals output by the set-top box can conform to various formats, such as: RGB, Svideo, composite video signals, etc., or can be various TV formats: NTSC, PAL, SECAM, etc. VES6100 also implements OSD (on-screen menu display) function.

    On the uplink channel, the information sent by the user, such as the selected TV series title information, is modulated - usually QPSK modulated (QPSK has strong anti-interference ability) and then sent to the TV station.

2 Demultiplexing unit

    VES2700 includes two independent microprocessors: (1) The customized RISC microprocessor is used for demultiplexing, that is, the transmission demultiplexing subsystem; (2) ARM703_t Host is responsible for the operating system and OSD, controlling I/O operations, etc. . The two processors work in parallel with no competition for resources. The 4K-byte Cache of ARM703 can access part of the code in a single instruction cycle. Advanced memory management mechanisms ensure that code, such as real-time operating systems, is kept in Cache.

    VES2700 has 4 independent high-speed buses to prevent bottlenecks. The 4 buses are: (1) channel data input bus; (2) bus connected to the DRAM controller; (3) ARM703_t Host bus, this bus is connected to the I/O bus and its peripheral interface; (4) connected to each A peripheral I/O bus.

    VES2700 provides dedicated hardware to support a variety of software functions, such as CRC check, transmission filtering, IR control and other functions. The library provided by the ARM703_t microprocessor can realize the software Modem function.

    The transmission/demultiplexing subsystem adopts a customized, high-performance RISC processor, which has its own dedicated 128B instruction SRAM and 512B data SRAM, processing MPEG2 transmission code stream and PES at a rate of 60Mb/s, and Parse into MPEG2 package, transmit the corresponding data to the video, audio, text, application information and other queues (located in external DRAM), and support CAS (Conditional Access System) management and loss Packet detection, PCR recovery, video and audio synchronization and other functions. The unified memory structure meets the needs of the transmission/demultiplexing subsystem and ARM703. RISC supports 32 different queues. The memory controller manages each queue through the queue head and queue tail pointers. The MPEG 2 decoder (VES6100) reads data from these queues.

    Video queue operation model: In order to write video data into the video queue, RISC writes the "0" queue number and valid data into the DRAM cache. When there are the same queue numbers, the memory controller will: (1) distinguish the relevant queue head pointer; (2) write data to the DRAM location pointed by the head pointer; (3) update the head pointer.

    During system initialization, ARM703-t downloads microcode from external memory (Flash Memory) to the on-chip dual-port SRAM. RISC executes microcode in SRAM at a clock rate of 40.5MHz. The transmission/demultiplexing unit can process 32 PIds (Packet PIDs) at the same time, supports transport packets and their payload data, PES packets and their payload data, and outputs program flow packets.

    The transmission/demultiplexing processor and ARM703-t share 2 memories for storing code and data tables. The RISC instruction RAM (I-RAM) occupies the initial 1.25KB address space. The ARM703 can read and write to the I-RAM, while the transmission/demultiplexing processor RISC can only read and write to the I-RAM. Read but not write. RISC data RAM (D-RAM) accounts for 512B. D-RAM is a dual-port access memory that can be read and written by RISC and ARM703. These two RAMs are mapped to the address spaces of ARM703 and RISC.

    Code and data can be downloaded using the following steps:

    (1) After starting, pause the transmission/demultiplexing processor by setting the stop bit of the RISC control register, write the code into the RISC SRAM, and restore the stop bit; (2) If RISC is running, stop the packer first, and then stop RISC ( Set the stop bit) and then write the new code to the RISC SRAM.

3 MPEG A/V decoder interface

    VES6100 requires external SDRAM to work and supports up to 32Mbit SDRAM, the size of which depends on the resolution and operating mode requirements. It also supports composite video, S-video, stereo, analog and digital IEC958 audio output. In the VES2700's A/V operating mode, video and audio can be selected as serial or parallel.

    The system adopts the serial video and serial audio mode because it is the most convenient to interface with peripherals at this time, and the OSD has the largest bandwidth. According to the selected mode, in this design, the A/V operation mode register is set as follows:

    0x1C=0x1800

    0x50=0x0040

    0x70=0x0042

    The connection between VES2700 and VES6100 is shown in Figure 2.

4 VES6100 processing of video signals

    The VES6100 chip is an MPEG2 decoder, and its internal structural block diagram is shown in Figure 3.

    The chip includes 3 subsystems:

    ·MPEG1/2 audio/video decoder;

    ·OSD subsystem;

    ·NTSC/PAL/SECAM encoder.

    Among them, the modules closely related to video signals are as follows:

    Video/Audio Streaming Processor VASP

    VASP decodes video and audio data. In video mode, VASP decrypts fixed-length codes and variable-length codes from the video stream in a hierarchical manner according to MPEG1/2 syntax, then translates these codes into instructions and data (8×8bit DCT data blocks), and transmits them to MSP. VASP also performs error detection and masking as well as inverse quantization of decoding coefficients.

    MPEG signal processor MSP

    As a slave unit of VASP, MSP receives the inverse quantization coefficient and a series of instructions from VASP, and performs all digital signal processing tasks related to MPEG1/2 decoding, including:

    ·IDCT (inverse DCT transform);

    ·Two-dimensional half-pixel filter calculation;

    ·Block reconstruction algorithm and motion compensation.

    The output of MSP is pixel data in 4:2:0 format, which is stored in external SDRAM for display purposes.

    Video image processor VGP

    VGP processes the decoded video data, such as converting 4:2:0 video format into 4:2:2 video format. It also performs image overlay, OSD and other functions.

    VES6100 works as a slave device of the microprocessor (VES2700). After power-on, VES2700 initializes VES6100 and programmable registers, and transmits compressed video/audio data to the serial port or 8-bit wide parallel port. The VES6100 then independently processes the compressed video stream in decoding mode. The microprocessor controls the setting register and responds to interrupts. The running status of the VES6100 can be obtained by reading the status register.

4.1 Video input

    MCB (Memory Controller and Microcontroller Interface) transmits the compressed video stream from the on-chip CDIF (Compressed Data Input FIFO) to the VCD B (Compressed Data Buffer, located in SDRAM). When VCDB reaches the upper limit mark, MCB generates an upper limit mark interrupt and the microprocessor stops data transmission. MCB passes the compressed video data to VASP. When VASP processes compressed data, MCB reads the data from VCDB and writes it to CDOF (Compressed Data Output Queue). If VCDB falls below the lower limit mark, the microcontroller resumes transmitting data. When VCDB reaches the lower limit flag, MCB generates a lower limit flag interrupt.

4.2 PES parsing process

    Before the video decoder extracts the header information, including PTS (display time tag), SCR (system reference clock), and compressed video data stream, the PES layer data analysis module has completed its positioning. This block is controlled by the microprocessor's decode control register. If the PES layer decoding mode is invalid, the compressed data is stored directly into SDRAM.

4.3 Start code search

    The block start code to be matched is located at the front end of VASP, and the compressed data stream is processed byte by byte. When the microprocessor requires a start code match, the start code matching logic begins to search for the start code until the match is successful. Typical start codes include sequence start codes, group start codes and image start codes. There are two types of start code searches: block search and non-block search. In non-block search, the video decoder continues decoding even if the start code is found; in block search, it stops the decoding process once the start code is found. When fast decoding is required, such as channel switching mode or still image capture mode, the sequence start code search method is used.

4.4 Video decoding

    VASP and MSP perform MPEG1/2 decoding operations, including VLC decoding, inverse quantization, half-pixel filtering, block reconstruction, and writing the reconstructed block into the SDRAM frame store. Decoding must be synchronized with display.

    The general decoding process of VES6100 is shown in Table 1. Events in the same column are processed simultaneously. As can be seen from the table, the decoding order is not consistent with the display order.

Table 1 General decoding process of VES6100

4.5 Video output

    MCB transmits the display frames stored in SDRAM to the video processor. The video processor converts the 4:2:0 decoding format into NTSC/PAL CCIR601 format.

4.6 Video stream error masking

    VES6100 can detect the following errors in video streams:

    ·Illegal syntax;

    ·In the 8×8 block, the number of coefficients is greater than 64;

    ·Bit errors in the data stream;

    ·The macroblock sequence number is wrong.

    Once VES6100 detects these errors, it takes masking measures to reconstruct the macroblock (copy the corresponding macroblock of the previous frame) until the next slice (slice) start code or image start code is detected. If there is a masking vector in the compressed data stream, it will be used as a reference for reconstructing the macroblock, otherwise a zero-valued motion vector will be used. If the macroblock sequence number is wrong, VES6100 discards data until the image start code is detected and continues normal decoding.

5 Audio and video synchronization

    The basic idea of ​​achieving video and audio synchronization is to recover a clock from the decoding end that is consistent with the encoding end. The video PTS and audio PTS are based on the same time base. Therefore, if the video PTS is synchronized with the system clock and the audio PTS is also synchronized with the clock, the video and audio will be synchronized.

    VES6100 obtains PCR (program reference clock) information from the code stream and uses them to adjust a 27MHz voltage-controlled crystal oscillator at the decoding end to obtain a system clock consistent with the encoding end. After this clock is divided by 300, it is used as the operating frequency of a 90kHz local counter, and the first PTS value obtained is used as the initial value of this counter. When outputting images and sounds, the value of this counter represents the current frame Actual output time. This time can be compared with the expected output time (PTS) to determine whether it is synchronized and determine synchronization measures.

    VES6100 has two audio and video synchronization modes: automatic mode and manual mode. Both synchronization modes are managed by the memory control block. The synchronization algorithm is based on two parameters: SCR (system reference clock) and PTS in MCB. SCR is similar to PCR. It is also a time stamp that encodes the timing of the bit stream itself. It can also be derived from the common time base used by the video and audio PTS values ​​of the same program. The three related registers are: PTS_audio, PTS_video and SCR, each 33 bits long, where SCR can be used as a counter at 90kHz.

    Automatic mode is divided into two types:

    (1) When the system stream is used as the synchronization reference, the SCR is used as the standard clock, and the PTS and SCR of the video and audio are compared. When the difference between PTS and SCR is greater than the display time, a synchronization signal is generated to skip or repeat the current unit (video is 1 frame, audio is 2×32 samples/channel). This is the default mode of the set-top box.

    (2) When using the audio stream as the synchronization reference, the audio PTS is used as the standard clock. The video PTS is compared with the audio PTS. When the difference between the two PTS exceeds the display time of one frame of image, a video synchronization signal is generated.

    Manual mode: In this mode, audio and video decoding run freely until the microprocessor issues a skip/repeat command or provides audio PTS and video PTS and PCR.

    The difference between automatic mode and manual mode lies in the source of PTS. In automatic mode, PTS is extracted from the MPEG 2 code stream or from an external clock; in manual mode, the microprocessor provides PTS.

6 Software design

    Software programming is completed using ARM ANSI C language combined with ARM assembly language. It mainly includes the settings of each register in VES6100 and VES2700, the control and coordination of various peripherals by VES2700, and the preparation of OSD. Most functions can be implemented using API functions. Software debugging can be carried out through the JTAG port. By connecting the hardware circuit board to the computer, you can observe the memory allocation, the current value of the register, and the execution of the software on the screen.