Application of simulation analysis based on IBIS model in high-speed DSP system design

    Abstract: Through the simulation of signal integrity based on the IBIS model, this paper analyzes an example of successful application in the design of a high-speed 160MHz DSP (TMS320C6701) system, and explains the important role of simulation analysis based on the IBIS model in the design of high-speed and complex systems. and practicality, describing the general process of simulation analysis based on the IBIS model.

    Keywords: IBIS model signal integrity high-speed design simulation analysis

    For high-speed systems, it is now a common practice for designers to conduct simulation analysis on the design during the design process and solve signal integrity (SI) and timing issues before plate making to ensure the first-time success of the design as much as possible. Simulation analysis is a process in which the EDA tool uses the input device model data for analysis during the design process, and intuitively feeds back the successful design and problematic areas to the designer, and the designer modifies and improves the design based on the feedback information. However, early high-speed designers found that if there are thousands of wire nets on a PCB board, simulation analysis based on electrical models requires too much calculation and too much time, which is impractical. To this end, a new behavioral-level modeling method was developed, which is called IBIS (I/O Buffer Information Specification). on).

1 Signal integrity analysis based on IBIS model

1.1 IBIS model and SPICE model

    The basis of simulation analysis is device model, and there are two main types of device models. One that appeared earlier was the electrical model, such as the SPICE model. The SPICE model attempts to describe the actual electrical connections of the circuit. The initial purpose of developing this model is to provide a simulation environment for the design of integrated circuits. At present, its main application is still in the design and verification of IC. Since the SPICE model is not designed for PCB transmission lines and other larger structures, it is unrealistic to use it to verify larger line networks. In addition, because it requires describing the actual electrical connections of a circuit, chip manufacturers are less willing to provide models for fear of revealing their technology.

    Another type of model is the IBIS behavioral model, which describes the input and output behavior of the device under a specific load and a specific package rather than its actual electrical composition. Compared with the SPICE model, the advantages of the IBIS model are reflected in three aspects: First, because the IBIS model protects the private information of the internal circuit, it has the support of the chip manufacturer of the model; second, the IBIS model can be used for faster Simulation analysis (25 times faster than the SPICE model), this advantage becomes very important as the density of PCB boards becomes higher and higher, and more and more key lines need to be analyzed. Therefore, the IBIS model is supported by EDA tools Third, the IBIS model is easy to obtain (provided by the manufacturer or generated by oneself) and understood, and because it includes the nonlinear characteristics of the I/O structure, packaging parameters and ESD structure, the IBIS model can achieve accuracy comparable to the SPICE model. In addition, the IBIS model does not have the common non-convergence problem of SPICE. These advantages have earned it support from designers.

    Due to these advantages of the IBIS model, it has been rapidly developed and widely used in just a few years since its initial prototype was formed in 1993, and has become an international standard for signal integrity models.

1.2 Signal integrity analysis

    The so-called signal integrity analysis is to analyze whether the signal generated by the driver is complete after being transmitted to the load through the wire, and the degree of interference. In the past low-speed digital designs, designers mainly considered whether the logic was correct rather than the integrity of signal transmission. The copper wire connecting the driver to the load is considered a pure short. With the continuous pursuit of high-performance products and the rapid development of semiconductor technology, the speed of integrated circuits is getting faster and faster, and high-speed devices are becoming more and more common. Signal integrity issues have become the most important concern for designers in high-speed digital design. question. The speeds of various types of logic devices are shown in Table 1.

Table 1 Logic device speeds

    Theoretically, when the signal transmission delay is greater than 20% of the signal level conversion delay (edge ​​rate), the copper wire connecting the driver and the load will be regarded as a transmission line rather than a pure short line. At this time, attention must be paid to the signal of integrity. Taking the edge rate as 1ns as an example, if the trace delay is greater than 200ps, it is regarded as a transmission line, and 200ps only corresponds to a trace length of 1 inch. Devices with an edge rate of 1ns are now very common, and the edge rate of TMS320C6701 has reached 0.6ns. Therefore, in today's digital design, signal integrity analysis is almost unavoidable. Even if a slightly slower device is used, if the system composition is complex and the wiring is too long, signal integrity analysis must be performed.

    Signal integrity problems mainly arise from the steep edges of high-speed drivers. In addition, impedance mismatch and electromagnetic interference from adjacent line networks can also damage signal integrity. The main signal integrity issues are: overshoot and undershoot, ringing, non-monotonicity, and crosstalk, as shown in Figure 1. If these signal integrity issues are not carefully analyzed, examined, and resolved, system performance will be severely impacted. The purpose of signal integrity analysis is to discover signal integrity problems and resolve them as much as possible before actual physical implementation.

2 Signal integrity simulation analysis in an actual high-speed DSP system design

2.1 System composition

    The system is a radar signal processor. The DSP uses the TMS320C6701 recently launched by TI. The DSP is manufactured using a 0.18μm CMOS process, with a clock rate as high as 167MHz and a driver edge rate of 0.6ns. The system consists of two TMS320C6701s. Each DSP is configured with its own high-speed synchronous memory (167MHz SBSRAM) and asynchronous memory. The bus between the synchronous memory and the asynchronous memory is isolated by a driver. There are two ways to exchange data between two DSPs: one is to interconnect through a high-speed synchronous communication port; the other is to exchange data through FIFO. Use high-speed CPLD to complete decoding and other controls. Two high-precision 16-bit ADs are used to collect radar signals, and one high-precision 16-bit DA is used to output the processed signals. AD and DA are connected to their respective DSPs through FIFO. The design requirement of the system working clock is 160MHz, and the main components of its high-speed digital part are shown in Figure 2.

    The system consists of 435 components and has 4419 wire nets. There are not only many high-speed pure digital devices in the system, but also digital-analog hybrid devices and analog devices that are very sensitive to interference.

    The system includes 7 types of power supply networks, digital network: 1.8V, 3.3V, 5V and DGND, analog network: +5V, -5V and AGND. The PCB adopts an 8-layer design: 4 signal layers and 4 power layers.

2.2 Preparatory work before simulation analysis

2.2.1 Selection of EDA tools

    EDA tools include two parts: schematic diagram and PCB production and signal simulation analysis. Generally speaking, these two parts are relatively independent software. For high-speed design, you must first choose a good signal simulation analysis tool. Some signal simulation analysis tools are based on the IBIS model, and some are based on other models such as the SPICE model; the simulation analysis functions of some tools based on the IBIS model are incomplete; in addition, the signal simulation analysis tools and the schematic diagrams and PCB production used Whether there is a good interface relationship between tools is also a factor that must be considered.

    The schematic and PCB production tools used in this design are Mentor Graphics' BoardStation simulation analysis and ICX produced by the company. ICX is a powerful EDA tool based on the IBIS model, which consists of modules such as layouter, simulator, optimizer and synthesizer. The placer completes layout and layout analysis; the simulator completes full-featured signal integrity analysis and timing analysis. The analysis can be performed before wiring (pre_simulation) or after wiring (post_simulation) on); the optimizer can layout according to design requirements Optimization, topology optimization, wiring optimization and optimization selection of different types of logic devices; the synthesizer can complete automatic wiring driven by design rules.

2.2.2 Acquisition and verification of IBIS model

    Since the device model is the basis of simulation analysis, the IBIS model of the device used in the design must be prepared before conducting simulation analysis. The IBIS models of devices mainly come from device manufacturers. IBIS models of some general devices can also be obtained from EDA tool manufacturers. As the advantages of the above-mentioned IBIS models are widely recognized, it is becoming easier and easier to obtain device IBIS models. For those IBIS models that cannot be found, you can also generate them yourself through certain methods.

    The quality of the device model directly determines the credibility of the simulation conclusion. Therefore, before using the obtained IBIS model for simulation analysis, the quality of the IBIS model must be verified. Model verification can be carried out with the help of specialized tools. Generally speaking, the IBIS models provided by device manufacturers and professional EDA manufacturers are more reliable.

2.2.3 Division of key line networks

    For complex designs, the number of wire nets may be in the thousands. In order to shorten the design cycle, the critical and non-critical wire nets in the design should be divided before simulation analysis. The principle of division is mainly based on the device driver edge rate and operating frequency; line networks that are sensitive to delay, such as clock signals, and line networks that require high curves, such as FIFO read and write signals, even if the rate is not high, It should also be regarded as a critical line network; in addition, for non-high-speed line networks, if the topology is not good and the wiring is too long due to the complexity of the system, necessary simulation analysis should also be performed.

    In this design, the high-speed devices are: digital signal processor TMS320C6701, 133M SBSRAM GVT7118G36, high-speed CPLD EPM712 8STC-6, high-speed bus driver and buffer SN74LVT162244, SN74LVT162245 and SN74LVT125 constitute the line network of these devices The high-speed line network of this design , as shown in Figure 2. In addition, other signals such as the read and write clocks of AD and DA, the read and write signals of FIFO, are also regarded as key lines.

2.3 Simulation analysis at different stages

    ICX tools provide pre_simulation before routing and post_simulation after routing. After the schematic is completed, pre_simulation can be performed. The simulation analysis at this stage mainly guides the layout through signal integrity analysis (excluding crosstalk) before wiring, selects the type of logic device, and determines which signals need to be terminated. , which termination method is used and the resistance value of the termination resistor.

    After pre_simulation guides the completion of layout and routing, there may still be some signal integrity problems. Crosstalk between adjacent line networks (pre_simulation does not consider it) is the main cause of these problems. The post_simulation function is used to conduct further simulation analysis on the design after the wiring is completed. The analysis at this stage considers almost all practical factors including crosstalk. Based on the simulation results of post_simulation, the design needs to be finely adjusted in terms of wiring, line spacing, termination positions and termination values ​​to reduce signal integrity problems to an acceptable range.

2.4 Modify the design through simulation analysis

    The use of high-speed devices in design will produce many signal integrity problems that are difficult to solve with logic analysis. Using signal integrity simulation analysis based on the IBIS model can conveniently and intuitively provide the designer with information such as the location and extent of various signal integrity problems. By. The designer makes modifications to the problematic areas accordingly, and then performs simulation analysis on the modified design to verify the effect of the modifications. Sometimes this process needs to be repeated several times to obtain satisfactory results.

    In this design, many serious signal integrity problems were exposed during the first simulation analysis, such as excessive overshoot and undershoot, severe ringing, non-monotonic edges, and excessive crosstalk. By adding series terminations with different resistance values ​​at the driver end, adding parallel terminations with different resistance values ​​at the load end, adjusting the position of the terminations, modifying the topology of the traces, adjusting the dielectric thickness between the board layers and even replacing the logic device Type and other methods were repeatedly modified and simulated to verify, and finally various signal integrity problems were limited within acceptable ranges.

    Figure 3 shows the different results of the signal integrity analysis of the DSP1 data line D8 when the operating frequency is 100MHz before and after adding a 33Ω series termination at the driver end; Figure 4 shows the DSP1 data line D8 after reducing some board layers when the operating frequency is 100MHz. Different results of crosstalk before and after the thickness of the medium.

    For high-speed, complex digital systems, signal integrity simulation analysis based on the IBIS model is a powerful assistant in design. Especially when high-speed devices with no design experience are used for the first time in the design, simulation analysis is particularly important. In this design, with the help of signal integrity simulation analysis based on the IBIS model, many signal integrity problems were solved. The debugging was successful once after plate making, avoiding repeated copies that may be caused by signal integrity problems, and shortening the design cycle. .