New high-speed image acquisition based on FPGA technology

    Abstract: This paper introduces a high-speed graphics acquisition system with FPGA as the core chip. The graphics acquisition frequency can reach 13.5MHz. In this system, the latest video A/D chip SAA7111 launched by PHILIP Company is also used to convert the TV signal into a digital signal, and the FPGA is used as the controller to store the digital signal into the 256KRAM so that the DSP chip can preprocess it as needed. Extract useful data.

    Keywords: FPGA A/D video acquisition

    Modern graphics acquisition technology is developing rapidly. Various graphics acquisition cards based on ISA, PCI and other buses are already available in the market, but they are relatively expensive and have simple processing functions. Special needs cannot be well met, and subsequent processing is often required, which brings inconvenience to users with special needs. The image acquisition system composed of field programmable chips and DSP processing chips can be programmed on site according to different needs, and has the characteristics of good versatility and relatively cheap price.

    The system uses the latest video A/D chip 7111 launched by PHILIP Company to convert the full PAL TV signal output from the CCD into a digital signal. The FPGA is used as a sampling controller to store the eight-bit digital signal into the on-chip RAM. Subsequently, the DSP can be preprocessed according to specific needs to extract useful data (the amount of data is already very small), and then the required results are handed over to the computer for processing via the ISA bus to complete the interface function. Figure 1 shows the block diagram of the acquisition system.

1 A/D conversion of video signals

    The graphic object studied in this article is static and requires the collection of 512×512 grayscale images. A CCD camera can be used for image collection. The output of the CCD is in standard PAL format, so A/D conversion is required.

    The video A/D chip SAA7111 of PHILIP Company used in this system has four video inputs, and the anti-aliasing filter and comb filter are integrated into the chip, which brings great convenience. The field synchronization signal VREF, the horizontal synchronization signal HREF, the odd-even field signal RES1, and the pixel clock signal LLC2 are all directly derived from the pins, eliminating the need for the previous clock synchronization circuit design and improving reliability. The integration of phase-locked loop technology within the system greatly reduces reliability and design complexity.
There is a control word in 7111 that can directly control the effective time of line synchronization, so the line delay circuit can be omitted.

2 Logic control part

    The core control part of this system is implemented by an FPGA chip. Because FPGA chips have the characteristics of high speed, high reliability, short development cycle, and can be programmed according to on-site needs and can be erased and written multiple times, they are extremely convenient. With the improvement of modern technology, the cost of chip processing has been greatly reduced, reliability has been guaranteed, and the size and power consumption of the chip have been greatly reduced. In particular, 3.3V FPGA is now the main product promoted by manufacturers. And there is a continued downward trend. The development of modern high technology has made it possible and inevitable trend for FPGA to be used in electronic design.

    The sampling controller based on FPGA technology needs to generate numerous control signals. When the microprocessor issues a sampling command, the sampling controller starts sampling when the first frame synchronization signal arrives, and stores the frame data in SRAM. After the sampling is completed, it sends a sampling end ECO signal to the microprocessor. The sampling controller mainly implements three logic functions: address generator; handshake logic; RAM write timing.

    (1) The address generator consists of a counter, a part of D flip-flops and logic gates. Mainly has field delay function and address generation function. Since the captured image is a 512×512 square (this is due to the need for subsequent processing of the system), the output signal in the 7111 is a 720×625 rectangle, so the 7111 signal needs to be line delayed and field delayed.

    When the digital quantity is stored in the memory, since the full TV signal of the PAL system is separated into odd and even fields, the odd and even signal RES1 can be cleverly used as the address line. According to RES1 being the high bit of the vertical address or the highest bit of the address, the image in the memory can look like one image or be divided into upper and lower half-field images, as shown in Figure 2.

    Dual-channel technology can be used in the storage process, that is, two pieces of memory are used to store data at the same time. The data bus is increased from eight bits to sixteen bits, which can reduce the RAM write timing requirements by half. Of course, this requires data latching of the digital signal output by the 7111, so that the two bits of data can meet the RAM write timing requirements based on the same control signal, as shown in Figure 3.

    (2) Handshake logic is the interface between the sampling controller and the CPU. It is implemented by several D flip-flops and logic gates, as shown in Figure 4.

    When CS1 (positive pulse) starts sampling, D1 saves the signal. When the next field synchronization pulse arrives, D2 outputs a high level (that is, the VER sampling enable signal) to cause the line delay counter to start counting and at the same time reset D1 to ensure that it will no longer Take the second game. When the delay counter counts to the preset value, it generates the trigger signal TRI (positive pulse). At this time, VER is "1", then D3 is set, and the sampling enable signal SENB (active low) and the address strobe signal ABSW are output, so that the following The circuit is in the sampling state, the falling edge of the field synchronization pulse D3 flips, and the entire sampling control circuit is in the non-sampling state. D2 will become invalid only on the rising edge of the next field synchronization pulse. When SENB becomes invalid (that is, the rising edge of SENB), D4 is triggered to make Q valid, and an interrupt request INT is sent to the CPU. The CPU can clear this interrupt signal with CS2.

    (3) The RAM write timing circuit can be designed according to the specific requirements of the chip for write operations. The system sampling frequency is 13.5MHz (74.1ns). Using dual-channel technology can reduce the write timing by half, and the write frequency is 13.5/2 = 6.75MHz (148.2ns). SAA7111 provides a crystal oscillator frequency of 27MHz, so it takes four clock cycles to complete a write operation, and the minimum time unit of the timing sequence is 18.5ns (half cycle). According to the requirements of RAM write operation, the relationship between various control signals (WE, HS, VS, CS, SENB), clock signal (CLK), address signal and data signal can be designed. The RAM used in this system is IS61C1024, which can meet the system needs.

    The sampling controller plays an important role and is the core of the entire system; and the synchronous control logic is the control core of the sampling controller. Synchronization logic plays the role of coordinating the time relationship between row and field synchronization signals, address count clocks, SRAM write signals, and sampling data latch signals, and ensuring the timing coordination of each signal during SRAM write operations. Since the sampling frequency is as high as 13.5MHz, constant simulation and emulation are required during the hardware implementation process. Sometimes it is necessary to adjust the entire logic circuit, calculate delay time, solve competition and risks in the circuit, etc., all of which require the system to be modifiable. Good performance and programmable features. ASIC design based on FPGA technology meets the above requirements, takes advantage of on-site programmability, reduces design costs, and shortens development time, so system development is very convenient.

3 DSP processing technology

    In this acquisition system, DSP-based image processing technology has also been applied, especially in the problem of image pattern recognition, the hardware structure and distinctive programming instructions of DSP have been fully utilized. The typical algorithm for image pattern recognition is convolution operation, that is, multiplication and accumulation, which takes advantage of the strengths of DSP software and hardware. The traditional processing method is based on computer hardware and software. It takes 11 machine cycles for a computer to complete a multiply-accumulate operation, while it only takes 1 machine cycle for a DSP to complete the same operation. This system uses DSP chips to realize pattern recognition of images, improves the processing speed, solves the problem of slow image recognition speed that affects the entire image processing flow during image processing, solves practical problems, and achieves good results.