TMS320C2XX and its application in wideband constant beamwidth beamformer

    Abstract: This article introduces the structure, characteristics, development environment and development process of TMS320C2XX series microprocessor chips, and gives an application example of TMS320F206 in a broadband constant beamwidth beamformer. The chip has a 25ns instruction cycle, 32kW on-chip high-speed Flash Memory and a logic scan circuit compatible with IEEE standard 1149.1, making the system's software and hardware design and development very convenient. In addition, its rich on-chip resources and high The cost-effectiveness makes it have good prospects for promotion and application.

    Keywords: digital signal processing beamforming JTAG logic scanning circuit

    Since my country introduced foreign digital signal processing devices in 1984, digital signal processing technology has been promoted and applied in many fields and has achieved gratifying results. In particular, the TMS320 series products of the American TI Company have a large user base and have accumulated rich experience and technical support in their applications. In order to further meet the needs of DSP applications, TI has recently launched the TMS320C2XX series of products. Compared with the TMS320C2X series, it has been greatly improved in terms of speed, on-chip resources and cost performance. The speed has increased by 2 to 4 times, while the price has dropped by more than half. In addition, the on-chip resources are richer and the development environment More convenient. The functions of its command system have been enhanced and compatible with it, so that the rich technical support of TMS320C2X can be inherited and it can be easily upgraded to TMS320C2XX. It can be expected that the TMS320C2XX series will definitely replace the TMS320C2X series and be promoted and applied.

    The author of this article combines specific topics and applies the TMS320F206 microprocessor chip in the TMS320C2XX series products to a broadband constant beam width beamformer. Due to the TMS320F206's rich on-chip resources and good development environment, the circuit design is simple and reliable, and debugging is convenient; through online simulation through the JTAG interface, software development and debugging is fast; the constituted system has strong functions, fast speed, easy debugging, expansion, and operation Reliable and stable.

1 Introduction to TMS320C2XX

    One of the three main features of TMS320C2XX is the use of an improved Harvard structure. There are six independent buses on the chip (three internal address buses: PAB, DRAB, DWAB; three internal data Bus: PRDB, DRDB, DWEB) , not only makes the access of program memory and data memory independent of each other, but also makes the reading and writing of data memory independent of each other and can be executed simultaneously, thus greatly optimizing the computing processing capability. Figure 1 is the bus structure diagram of TMS320C2XX.

    The second feature of TMS320C2XX is that the on-chip resources are richer. There are four products in this series. In order to meet the needs of different applications, their on-chip resources are also different. Table 1 lists the main in-chip resources of these four products and their comparison with TMS320C25.

    The third feature of TMS320C2XX is the on-chip logic scanning circuit, which is compatible with IEEE standard 1149.1 and is connected to the external 14-pin JTAG interface through eight dedicated pins. The following work can be completed through the JTAG interface: (1) The chip pins can be tested; (2) The external Data space and I/O space can be detected; (3) The internal Flash Memory of the chip can be programmed; (4) Data can be loaded into the on-chip and off-chip RAM; (5) Online simulation can be performed. The above features bring great convenience to hardware debugging and software development.
TMS320C2XX has a total of 85 instructions, which not only covers all the functions of the 133 instructions of TMS320C25, but also the functions of the instructions have been enhanced and the content has been increased.

Table 1 List of main on-chip resources of TMS320C2XX

2 Development of TMS320C2XX

    The development process of TMS320C2XX is very similar to that of TMS320C2X. The convenience lies in the fact that the hardware circuit can be tested online and the software can be simulated online through the JTAG interface. The software development process is shown in Figure 2.

    There are two types of files that need to be edited here: one is the source file required by the application system (*.ASM); the other is the command file (*.CMD) for locating the source code. When writing the source program file, the size of the symbols must be distinguished. Write.

    The OBJ file generated by the assembler assembling the assembly source program is a common object file format (i.e. COFF file). For instructions, please refer to "TMS320 FIXED - POINT DSP ASSE" Chapter 2 of the book "MBLY LANGUAGE TOOLS GUIDE".

    The connection of the program is to use the DSPLNK connector to connect the COFF target files (one or more) to produce an executable output file. When connecting, DSPLNK calls the command file (*.CMD) to locate the target file. Commonly used connection formats are:

    DSPLNK DEM01 DEM02 DEMO. CMD -0 DEMO. OUT-M DEMO. MAP,

    where the input file is: DEM01. OBJDEM02. OBJ, the command file is DEMO. CMD, the output file is DEMO. OUT, the mapping file is DEMO. MAP.

    The software debugger will output the file *. OUT is transferred into the debugging environment for simulation operation for debugging. The debugging interface is friendly, easy to learn and use. For specific debugging steps, please refer to reference [2].

    There are three ways to use the user's object code in the target system. One is to customize the object code into the on-chip ROM (such as C204 and C209); the other is to program the object code into the on-chip Flash Memory (such as F206); It is to solidify the object code into EPROM (such as C203).

    If you want to program the target code into EPROM, you must first compile a format conversion file: Boot. CMD, and then run DSPHEX Boot CMD will *. OUT files are converted to *. bin file, and then use a programmer to program and burn it into EPROM.

    TMS320F206's on-chip 32Kw high-speed Flash Memory is a good on-chip resource, and the output file can be exported through the JTAG interface*. OUT is programmed into the on-chip Flash Memory and can be run online through the JTAG interface, making debugging very convenient. When programming the on-chip Flash Memory, you can compile a batch file*. BAT runs under DOS or WIN98 environment, and can also directly use the software provided by the manufacturer to program Flash Memory.

3 The application of TMS320C2XX

    will be introduced by taking the constant beam width beamformer of TMS320F206 in TMS320C2XX applied to broadband sonar as an example. Generally speaking, sonar beamwidth is related to frequency. In order to obtain a constant beam width in a broadband signal, we use different coefficients to correct the data in different frequency bands. In this way, for a line array with 16 array elements to obtain 16 beams with constant beam width in real time, a total of 256 "delay-weighted-sum" networks are required, and its total processing capacity should be greater than 1.7 billion times per second. Addition operations and corresponding data access. To this end, we use eight IMSA100 chips produced by the British INMOS company and eight TMS320F206 chips to form a processing array. The TMSA100 completes the delay correction, and the TMS320F206 completes the phase compensation and weighted summation.

3.1 Circuit design

    During circuit design, a piece of IMSA100 and a piece of TMS320F206 plus necessary peripheral circuits are used to form a logic module. Since the TMS320F206 chip contains 32Kw of Flash Memory that can store program codes, coefficients and parameters, coupled with the 4K on-chip DARAM, general-purpose I/O ports and other resources, the circuit is greatly simplified. In order to make full use of the device's processing capabilities and meet the system's real-time processing requirements, we designed the data buffer area in a ping-pong manner. The block diagram of the circuit module is shown in Figure 3.

    When making printed circuit boards, due to the simplicity of the unit module circuit, we built two beam processing modules on one circuit board, and eight modules shared four beam processing boards. The management and control of the beamformer, communication with the front and rear stages and data formatting are completed by two TMS320F206. The entire system consists of five circuit boards, including ten TM320F206, eight IMSA100 and corresponding peripheral devices. The entire system is fast, powerful, scalable and easy to debug. The maximum processing speed can reach 2.9 billion multiplication and addition operations per second.

3.2 Software design

    This system uses ten pieces of TMS320F206. Due to the modular design, the eight TMS320F206s in the eight beam processing modules have basically the same working process, except for the different coefficients and parameters. In this way, the software design and debugging tasks are greatly reduced, and the software design of each TMS320F206 also adopts modular design, and the corresponding command files are edited. Finally, the assembly, connection, and programming are compiled into a batch file, which can be executed in DOS Or under the WIN98 environment, with the help of the JTAG interface, the software can be simulated and run online. The debugging and modification of the software, parameter adjustment and coefficient correction can all be carried out online, thus greatly shortening the development cycle. There are two other pieces of TMS320F206, one is used for the control and management of the beamformer, and the other is used for data formatting and data exchange and communication with the front and rear stages.

    Due to the high cost performance and good development environment of TMS320F206, the system has the characteristics of high speed, scalability, easy scheduling, and easy modification.