Research on parallel I/O boot loading method of TMS320VC5402DSP

    Abstract This paper introduces the performance of TMS320VC5402 DSP chip, focuses on analyzing its on-chip ROM structure and parallel I/O boot loader, and gives a method of using 8031 ​​microcontroller to implement 8-bit parallel I/O boot loader. Practice has proved that this method has great flexibility and practicality.

    Keywords Digital signal processor (DSP) boot loader microcontroller

    TMS320VC5402 (hereinafter referred to as C5402) is a fixed-point digital signal processor (DSP) launched by Texas Instruments (TI) in October 1999 with extremely high cost performance (target price is only US$5). The main features of C5402 are as follows[1]:

·Operation rate reaches 100MIPS;

·Has advanced multi-bus structure, three 16-bit data memory buses and one program memory bus;

·40-bit arithmetic logic unit (ALU), including a 40-bit barrel shifter and two 40-bit accumulators;

·A 17×17 multiplier and a 40-bit dedicated adder, allowing 16-bit signed/unsigned multiplication;

·Integrate Viterbi accelerator to improve the speed of Viterbi encoding and decoding;

·Single-cycle normalization and exponential decoding;

·8 auxiliary registers and a software stack allow the use of the industry's most advanced fixed-point DSP C language compiler;

·Data/program addressing space 1M×16bit, built-in 4K×16bit ROM and 16K×16bit RAM;

·Built-in programmable wait state generator, phase-locked loop (PLL) clock generator, two multi-channel buffered serial ports, an 8-bit parallel HPI port for communicating with an external processor, two 16-bit timers, and 6 channels DMA controller;

·Low power consumption, the working power supply is 3V and 1.8V (core), especially suitable for battery-powered equipment.

It can be seen that compared with other chips in the TMS32054X series, C5402 has been welcomed by industry users as soon as it was launched due to its unique high performance, low power consumption and low price characteristics. However, its internal structure and on-chip mask bootloader program are quite different from other DSP processors in the C54X series [2], and most of its application objects require offline operation, such as set-top boxes. (STB), personal digital assistant (PDA) and digital wireless communications and other embedded systems. To this end, based on our practical experience, this article briefly introduces the C5402 Bootloader program analysis and implementation methods, and introduces the parallel I/O Bootloader method in more detail.

1 Several boot loading methods

The C5402 on-chip masked Bootloader is used to guide the user program from the outside into high-speed RAM during power-on reset to ensure that it runs at full speed. C5402 provides the following four Bootloader methods: 8-bit or 16-bit parallel EPROM method, 8-bit or 16-bit parallel I/O method, 8-bit or 16-bit serial port method and processor communication port (master port) HPI method.

After power-on reset, C5402 detects its MP/MC pin. If MP/MC="0", it enters the Bootloader program. After entering the Bootloader, if there is an INT2 request interrupt, it will enter the HPI boot mode. Otherwise, the boot mode selection word (Boot Routine Selection, BRS) of the I/O end with the port address 0FFFFH will be read. When BRS=XXXX00, enter the I/O or serial port boot mode. For example, when BRS=XXXX1000, enter the 8-bit I/O boot mode. When BRS=XXXX1100, enter the 16-bit I/O boot mode. Otherwise, enter the serial port boot mode. Line-of-mouth guidance. When BRS=XXXX01, enter the 8-bit EPROM boot mode; when BRS=XXXX10, enter the 16-bit EPROM boot mode.

2 C5402 on-chip ROM structure and parallel I/O boot loader analysis

C5402 provides a 4K×16bit mask ROM, whose specific contents are shown in Table 1. After C5402 is powered on and reset, if MP/MC="0", the Bootloader program will start running from the F800h address. Before entering the 8-bit parallel I/O boot program, C5402 needs to conduct a series of communications with the external I/O. The program block diagram is shown in Figure 1.

The following is the 8-bit parallel I/O bootloader snippet:

Line number source program annotation

(label) ..

END; End of reading user code

                ;And transfer to execute the user program

1 CALL (21); call the data reading subroutine

2 STL B,61h; Contents of B→unit 61H

3 CALL  (21); Call the data reading subroutine

4 STL B,61h; Contents of B → Unit 62H

5 CALL (21); call the data reading subroutine

6 BC (END), BEQ; ends when B＝0

7 SUB #01h,0,B,B; B－1→B

8 STLM B,BRC; B→BRC

9 CALL (21); call the data reading subroutine

10 STL B, 68h; content of B → unit 68H

11 CALL (21); call the data reading subroutine

12 ADD 68h,16,B,B; add B→B after 68H shift

13 LD B,0,A; B→A

14 RPTD (20)-1; cycle 15-19              

15 CALL (21); call the data reading subroutine

16 SSBX XF; XF＝1

17 BC  (17), BIO; if BIO=0, wait

18 WRITA B; write the content of B to *A

19 ADD #01h,0,A,A; A+1→A

20 B  (5) ; jump to label 5

       . 

２１ SSBX XF；XF＝1

２２ BC(22),BIO; BIO=0 then wait

23 RXBX XF; XF＝0

24 BC(24),NBIO; BIO=1, then wait

25 POETR 0000h,B; read 0 address port → B

26 SFTL B,8,B; shift B left by 8 bits→B

27 SSBX XF; XF＝1

28 BC(28),BIO; BIO=0 then wait

29 RXBX XF; XF＝0

30 BC (30),NBIO; BIO=1 then wait

31 PORTR 0000h,68h; read 0 address port→68

32 ANDM 000ffh,68h; logical AND

33 OR 68h,B ；Logical OR → B

34 RET; return

In the above program, the END label gives the entry address that is transferred after the I/O read operation is completed, and then goes to the entry addresses given by 61H and 62H to execute the user program. Lines 1 to 4 read the entry address; lines 5 to 8 read the data block length; lines 9 to 13 read the first address of the data block; lines 14 to 20 read the data block. In order to better understand the working process and principle of this program, Figure 2 shows the 8-bit parallel I/O Bootloader program flow chart. Lines 21 to 34 are subroutines for reading data. In this program, XF and BIO signals are used to conduct handshake communication with external I/O. The signal timing is shown in Figure 3.

3 Implementation of C5402 parallel I/O boot loading method

3.1 Hardware circuit analysis

In order to meet the timing requirements of the C5402 DSP 8-bit parallel I/O bootloader, this article uses the 8031 ​​microcontroller as the intelligent I/O component. Figure 4 is the connection circuit diagram of C5402 and 8031. In the picture, U3 is TMS320VC5402DSP, U? It is an 8031 ​​microcontroller, U1 and U2 are both SN74AHC245, and the EPROM in the microcontroller system

Circuit not shown.

The DIR pins of U1 and U2 are grounded, and the data transmission direction is B→A. B7~B4 and B2~B0 of U2 are connected to ground, B3 is connected to DVDD (3.3V), and /CE is connected to the system reset signal, ensuring that U2 provides 00001000B data to C5402 during power-on reset, allowing it to enter 8-bit parallel I/O Boot mode, and when the reset signal is invalid, the /CE = "1" chip select signal of U2 is invalid and leaves the system. The function of U1 is a data buffer and a level converter. The VCCD terminal of U1 is connected to 4.3V. Its function is to convert the TTL level output by the 8031 ​​into a CMOS level acceptable to the 5402; the /CE of U1 is disconnected from the P3 of the 8031. 3(/INT) pin remains high from system reset until CLR P3.3 is executed. During this period, U1 is invalid, ensuring that U2 normally supplies the data required by 5402. P3.0 (RXD) and P3.1 (TXD) of 8031 ​​are used as handshake signals and are connected to /BIO and XF of C5402 respectively. JP3 and JP4 allow users to jumper to select the system clock of C5402 and select the operating mode of C5402.

3.2 Programming

Based on the above analysis, this article designs the following 8031 ​​assembly program. First make /CE of U1 valid, then wait for XF of C5402 to be low level, and after XF="0", make P3.1 of 8031="0", that is, BIO="0", C5402 enters the waiting data state. After the data is sent to the data bus, let BIO="1" notify C5402 to read the I/O port data. In the program, the first 22 bytes of the code defined by UC are the contact code with C5402, and starting from the 23rd byte are the user program codes. ··

    CLR P3.3; Make U1(AHC245)CE=0

W1: JB P3.0, W1; XF=1 waiting

    CLR P3.1; Make BIO=0

    MOV R4,#00H; initialize index register

W2: JNB P3.0, W2; XF＝0 wait

    MOV DPTE,#UC; points to the first address of user code

    MOV A,R4; index to send A

    MOVC A,@A+DPTR; get user code

    MOV P1,A; sent to data bus

    SETB P3.1; Make BIO=1

W3: JB P3.0, W3; XF=1 waiting

    CLR P3.1; Make BIO=0

    INC R4; points to the next code

    CJNE R4,#0FFH,W2; Unfinished restart

UC: DB 08H,0AAH,00H,00H

      DB 00H,00H,00H,00H

      DB 00H,08H,00H,25H

      DB 00H,00H,00H,80H

      DB 0F4H,95H,0E9H,27H

      DB 0F3H,10H; the above is the contact code with C5402

                  ;User program code

TMS320VC5402 DSP is the latest member of the C54X family and even TI's DSP family. It is being accepted by more and more users for its extremely high cost performance. This article uses the cheap and versatile 8031 ​​microcontroller to implement the C5402 8-bit parallel I/O bootloader function. On the one hand, it can well solve the data transmission problem between fast DSP and slow I/O (EPROM); on the other hand, C5402 After the bootloader is successful, 8031 ​​can also be used as an "assistant manager", thus greatly improving the flexibility and practicality of the system. have a broad vision of application.