A simple test method for ADSP21062 signal processing board

    Abstract: Aiming at the development and research of ADSP2106x processing system, a simple and easy test method is proposed. This method can not only determine whether the DSP can work normally, but also test the effectiveness of multi-processor transmission of signals through the Link port. The proposed test method has been verified in the debugging of the radar signal processing system based on ADSP21062.

    Keywords: DSP test solution radar signal processing system

ADSP2106x SHARC is a high-speed 32-bit digital signal processor suitable for voice, communications and image processing. This chip is a complete single-chip system developed based on the ADSP21000 series DSP chip, adding a dual-port on-chip SRAM and integrating I/O devices. With its on-chip instruction cache, the processor can execute every instruction in one clock cycle. ADSP2106x SHARC embodies a new integration standard for digital signal processors, combining a high-speed floating-point DSP main processor with integrated on-chip components, including a host interface, DMA controller, serial port and connectivity port . Because of its fast processing speed and easy connection and communication of DSP multi-processing systems, it has been developed and applied in more fields [1]. But how to debug the processing system based on ADSP2106x is a key issue that people must solve when applying this chip. This article proposes a simple and easy test method, and achieved success in debugging the radar signal processing system based on ADSP21062, verifying the feasibility of the method.

1 Introduction to radar signal processing system design

We designed a radar signal processing system using the ADSP21062 processor. This system can work independently or communicate with other DSPs through the Link port. ADSP21062 uses the JTAG interface to connect with the EZ-ICE emulator to implement system simulation and testing. The circuit structure of the system is shown in Figure 1.

The EZ-ICE emulator applies the IEEE1149.1 JTAG test standard to monitor and control the work of the target board processor. The test head of the EZ-ICE emulator is connected to the CLKIN (optional), TMS, TCK, TRST, TDI, TDO, EMU and GND signals of the target board processor through a 14-pin connector. A 14-pin interface is designed on the circuit board, and its signal interface is shown in Figure 2.

2 Circuit testing

Circuit testing mainly uses EZ-ICE simulator. The emulator is inserted into the ISA slot of the PC and connected to the ADSP21062 processing system through the JTAG port. The Emulator control interface can be used to monitor the operation of the DSP system in real time on the monitor of the PC. ADSP2106x provides two sets of software, Simulator and Emulator. Their interfaces are exactly the same, except that one does not require hardware and the other requires hardware. The test program can be assembled by the Assembler first, and then passed through the Simulator. Finally, under the control of the Emulator interface, the executable file (.EXE file) generated by assembly and the assembled structure file (.ACH file) can be loaded to implement hardware testing and simulation.

2.1 Basic operations of hardware testing

When testing the hardware, first perform simple operations on the internal control, status register and memory of the memory to ensure that the communication between the EZ-ICE emulator and the processor is normal.

There are generally two types of operations on registers: bit operations and word operations [2~3].

(1) Bit operation: The bit operation of the register is mainly used for BIT SET and BIT CLR.

For example: BIT SET MODE2 0x00000001;

BIT CLR MODE2 0x00000001;

The above operation sets or clears the first bit of MODE2 without affecting other bits.

(2) Word operation: Use DM() addressing instruction for word operation of register.

For example: R0=0x00000001;

DM(SYSCON)=R0.

The above operation sets the first bit of SYSCON and clears the other bits.

The DM() instruction is used to address the memory operation. Direct addressing, indirect addressing and Indexed addressing.

For example: R0=0x23;

DM(0x00030000)=R0.

The above operation will put 0x23 into the address of 0x00030000.

2.2 System operation test

Design an operation on the four indicators of the FLAG bit to flash alternately to verify whether the ADSP21062 processor can operate normally. The program adopts the middle method, using the timer to generate two interrupts TMZHI and TMZLI when it overflows. One interrupt service program sets the indicator lights of FLAG0 and 1 to be on, and the indicator lights of FLAG2 and 3 are off; the other interrupt service program sets the opposite situation. The two service programs are executed alternately, and the alternating interval is determined by the initial value of the timer. The program flow chart is shown in Figure 3.

Since the MODE2 register is cleared when the processor resets the system, making the FLAG pin an input, the processor cannot change its state. Therefore, the main program needs to initialize it to make the FLAG pin an output, and then change the status of FLAG in the ASTAT register. Likewise, the timer must also be set.

(1) Timer setting:

BIT SET MODE1 0x1000; (open global interrupt)

BIT SET MODE2 0x20; (open timer)

BIT SET IMASK 0x10; (open TMZHI interrupt)

(2) Setting of FLAG bit:

BIT SET MODE2 0x78000; (set to output)

BIT CLR ASTAT 0x180000; (FLAG0,1 is on)

BIT SET ASTAT 0x600000; (FLAG2, 3 off)

This program can pass JTAG simulation test, use a general programmer to write this program into EPROM, and then let the system work alone to verify whether the system can boot and work normally. After powering on, the four indicator lights flash alternately, and it is verified that the system has successfully completed the boot and is working normally.

2.3 Link port test

Use a transmission line to connect the two Link ports of the processor together, then let one Link port send data and the other to receive data. Use the Emulator (JTAG) to test it in a single-step execution manner and observe the sending and receiving process.

(1) Link port transmission rate setting:

R0=0x00006000;

DM(LCOM)=R0; (2x rate)

(2) LBUF settings:

R0=0x0003fe8f;

DM(LAR)=R0; (LBUF1 is for Link port 1, LBUF2 is for Link port 2)

(3) Open Link port:

R0=0x00000190;

DM(LCTL)=R0;(Link port 1 sends, Link port 2 receives)

(4) Transmission operation:

R0=0x12345678;

DM(LBUF1)=R0;(Link port 1 sends 0x12345678)

R1=DM(LBUF2); (Data received by Link port 2)

After testing, the Link port works normally. You can see through the Link port control window of the Emulator: when the Link port setting is completed and the DM (LBUF1) = R0 instruction is executed, you can see that the status of the Link port 2 buffer (through the LxSTAT register) is that there is one data; when R1 is executed =DM(LBUF2) instruction, the status of the Link port 2 buffer is empty, and the value of the register R1 port is the content of the Link port 1 buffer (LBUF1). It is proved that data can be transmitted smoothly through Link port 1 to Link port 2, and communication between processors can be completed through Link port.

2.4 Execution time of DSP algorithm

A DSP algorithm written in assembly is put into the system for execution through the EZ-ICE emulator. The clock (instruction) counting function provided by the Emulator can know the actual execution time of the algorithm in the processor. There is a clock count (Cycle Count) in the count window of the Emulator, which records the number of clock cycles used from the beginning to the stop of the program. Multiply the number of clocks (Cycle Count) by the clock cycle to get the total execution time. time.

In view of the development and research of the ADSP2106x processing system, this article proposes a simple and easy test method that can not only determine whether the DSP can work normally, but also test the effectiveness of information transmission through the Link port when multi-processors are interconnected. The proposed test method was verified in the debugging of the radar signal processing system based on ADSP21062 we developed.