PCI bus interface technology and its application in high-speed data acquisition system

    Abstract: The implementation of a high-speed data acquisition and transmission system based on PCI bus is discussed. The performance and three transmission modes of PCI bus controller 9054 are discussed. The hardware implementation of the system and the design of data transmission using DMA transmission method are provided.

    Keywords: PCI bus PCI 9054 bus controller DMA

Data acquisition is a very important link in digital signal processing. For different tasks, the technical indicators to be achieved for data collection are also different. For transient signals, radar signal and image processing require ultra-high-speed acquisition rates of several MB/s or even tens of MB/s. Most of the data acquisition cards currently used in PCs are based on the ISA bus. The biggest disadvantage of this structure is that the transmission rate is too low and cannot realize high-speed data transmission. After the launch of the PCI bus, it has been favored by the computer and communications industries for its outstanding performance. It will replace the previous bus and become the cornerstone of external components for high-end machines and high-performance workstations. As a local bus, PCI interfaces with the processor and memory bus on one side; on the other side it provides a high-speed channel for peripheral expansion. The 33MHz, 32-bit PCI bus can achieve a data transfer rate of 132MB/s; the 64-bit PCI bus doubles the performance. The development of data acquisition equipment based on PCI bus is an inevitable requirement for technological development. In actual work, the PCI bus is used to directly transfer the collected data to the system memory, which can effectively solve the real-time transmission and storage of data and provide convenience for real-time processing of signals.

1 Structure and function of data acquisition system

This data acquisition system is applied to the processing of radar video echo signals. The signal consists of two orthogonal video echo signals, so dual channels are used. Acquisition indicators: 2-channel acquisition signal, sampling rate is 40M samples, A/D sampling word length is 10 bits. The word length of each digital signal is 16 bits, and the two combined channels have a total of 32 bits. The 32-bit data is transferred to different areas of the system memory for subsequent processing. The system design is based on the PCI bus controller and transmits 32-bit data to different areas of the system memory through DMA. The main functional modules include: PCI bus controller, dual-port SRAM, acquisition control chip EPLD, and A/D part. The system block diagram is shown in Figure 1.

2 Implementation of PCI bus controller

The PCI bus is a bus that multiplexes address/data, command/byte select signals. It uses a master-slave signal two-way handshake to control data transmission, and its interface circuit design is not much different from the traditional bus interface circuit design. Generally speaking, a PCI interface circuit should complete the following functions: (1) Address decoding and command decoding, because the PCI bus can be decoded in forward mode and negative mode. Therefore, users should choose the appropriate decoding method according to the application situation. Generally, forward decoding is selected; in order to ensure that no address conflict occurs, it is best to use full address decoding; the command signal line C/BE[0~3] must be able to be decoded. (2) Address generation circuit. The burst transmission mode of PCI includes an address cycle and several data cycles, so the PCI interface circuit must contain a high-speed address generation component to provide the connected address to the downstream application circuit. (3) Control signal generation. Data transmission on the PCI bus is basically controlled by four signal lines: FRAME, IRDY, TRDY and DEBVSEL. Therefore, these control signals must be generated according to the busyness of the master and slave devices. In addition, the PCI interface circuit should also complete the functions of address latch and data separation, command latch and byte selection signal separation. It is worth noting that the signal load capacity in the PCI specification must be taken into consideration when designing this function. There are generally two ways to implement a PCI bus controller: using programmable devices and dedicated interface chips. The advantage of using programmed logic devices such as EPLDs and FPGAs is their flexible programmability. The dedicated chip can realize the complete PCI main control module and target module interface functions, and convert the complex PCI bus interface into a relatively simple interface. Users can focus on application design instead of debugging the PCI bus interface, significantly shortening development time. This design uses PLX Company's PCI9054 to implement the bus controller.

3 Introduction to PCI 9054

PCI 9054 is a 32-bit/33MHz universal PCI bus controller dedicated chip. The chip complies with PCI bus specification version 2.2 and has a burst transfer rate of 132MB/s. The local bus supports multiplexed/non-multiplexed 32-bit addresses/data, and can be one of M mode, C mode, and J mode. There are 6 programmable FIFOs inside the PCI 9054 to achieve zero-wait burst transmission and asynchronous operation between the local bus and the PCI bus. 9054 supports master mode, slave mode, and DMA transmission methods, and can be used for adapter cards and embedded systems. The structural block diagram of PCI 9054 is shown in Figure 2.

 

Master mode operation allows the local CPU to access the memory and I/O interfaces on the PCI bus. Mode selection must be enabled in PCI command registers, such as PCI master memory and I/O range registers, PCI base address registers, master configuration and command registers, etc. Master mode operations include PCI main device memory and I/O decoding, PCI main device memory and I/O configuration access, PCI dual address cycle access, PCI main device memory write and invalidation and other operations.

*Operation from mode

The slave mode allows the master device on the PCI bus to access the configuration register or memory of the PCI 9054 on the local bus, and supports burst and single-cycle active mode transmission. PCI 9054 supports burst or single-cycle memory mapped access and I/O mapped access from the PCI bus to the local bus through a 16-word PCI slave read FIFO and a 32-word PCI slave write FIFO. The PCI base address register is used to set the addresses of PCI memory and I/O space. Slave mode operations include delayed read operations, read ahead operations, etc.

*DMA operation

The PCI 9054 has a powerful dual-channel scatter/gather DMA controller that supports high-speed transmission of PCI host and adapter memory. Two independent DMA channels can transfer data from the local bus to the PCI bus and from the PCI bus to the local bus. Each channel includes a DMA controller and a dedicated bidirectional FIFO. Both channels support block transfers, scatter/gather transfers, application or no EOT transfers, etc. Mode selection must be enabled before the PCI 9054 becomes a PCI bus master. The inter-master enable bit (PCICR[2]) is enabled. In addition, both DMA channels can be programmed to achieve 8, 16 or 32-bit local bus bandwidth; enable/disable internal wait cycles; enable/disable local bus burst transfers; perform PCI memory write and invalid operations; set PCI interrupts (INTA) or local interrupt (LINT), etc. Figures 3 and 4 respectively describe the DMA data transfer operation logic from PCI to the local bus and from the office bus to the PCI bus. 4 Sampling control and driver design

Based on development cycle and cost considerations, this design uses DMA transmission mode. After starting the sampling, the 1KB×8 dual-port SRAM IDT7130 is used as the data buffer between the data acquisition front-end and the PCI bus, and the PCI 9054 is used as the master control device, using its DMA channel for data transmission. When the dual-port SRAM collects 1KB of data, a local bus interrupt is generated through EPLD (EPM7128). After PCI9054 obtains control of the local bus, it reads 1KB of data into the dedicated FIFO for DMA transmission according to the start bit of DMA. PCI 9054 Apply to occupy the PCI bus, and after obtaining control of the PCI bus, write the data into the PCI bus storage space to achieve one-time sampling and transmission.

Programmable logic device (EPLD) is used to implement the I/O logic, transmission control logic, interrupt logic of PCI 9054 and dual-port SRAM, as well as the front-end control of the data acquisition channel by the host.

Another key issue for PCI data acquisition cards is driver development. The device driver provides a software interface linked to the PCI board, a dynamic link library with a file extension of .SYS. In Windows98 and Windows2000, device drivers must be designed according to the Windows Driver Model (WDM). The key of the device driver is how to complete the hardware operation. The basic function is to complete the initialization of the device, read and write operations on the port, interrupt device and response and interrupt calls, as well as direct reading and writing of the memory. This design uses KRF-Tech's Windriver to write device drivers. Windriver writes API function packages for the special interface chips of PLX and AMCC, which reduces the difficulty of development.

With its powerful functions and simple user interface, PCI 9054 provides a simple method for the development of PCI bus interface. Designers only need to design the local bus interface control circuit to achieve high-speed data transmission with the PCI bus. In the high-speed data acquisition system, the high-speed characteristics of the PCI bus are used to transmit and store the collected data in real time, which effectively solves the real-time problem of data transmission and processing. With the popularization and application of PCI bus, the design of acquisition system based on PCI bus has very broad prospects.