Design of UARTl6550 Based on FPGA

Wang Jianwei, Wang Houjun, Wang Yi, School of Automation Engineering, University of Electronic Science and Technology of China

1. Introduction

UART (Universal Asynchronous Receiver/Transmitter) is a chip used to control the communication between CPU and serial devices, converting the parallel data transmitted by CPU into an output serial data stream. It converts the serial data from outside the system into bytes for the devices that use parallel data inside the system. It can add parity bits and start/stop marks to the output serial data stream, and perform parity check on the data stream received from the outside and delete the start/stop marks. Common UARTs include INS8250, PC16450 and PCI6550. Among them, 16550 has 16 B FIFO for both sending and receiving, which provides more buffer space for coordinating the rate matching of the sending and receiving ends, and can also improve the efficiency of CPU use, thereby improving the overall performance of the system.

2 Basic Structure of UART16550

As shown in Figure 1, the basic structure of UART16550 consists of seven parts: CPU interface module, baud rate generator, FIFO controller, transmit/receive FIFO and transmit/receive module.

The CPU configures the entire UART through the CPU interface module of the UART. The baud rate generator generates the required baud rate after the CPU writes the initial value, and controls the sending and receiving modules to work at the set baud rate. The CPU writes the 8-bit data to be sent into the sending FIFO through the interface module. At the same time, the sending module starts to read the data in the FIFO, and adds the start bit, parity bit and stop bit to transmit it to the serial receiving device in a serial transmission mode. The receiving module monitors the serial input port at all times. When it finds that there is data being sent, it immediately starts the receiving module to start receiving data and effectively judges the parity bit to detect the correctness of the data. Finally, the remaining 8 bits of data are placed in the receiving FIFO, and the CPU is notified that there is data coming in for reception. The data transmission format of the asynchronous serial communication protocol is shown in Figure 2.

The UART16550 can send data bits of 5 to 8 bits, and can select odd parity, even parity or no parity bit. The stop bit can be agreed to be 1, 1.5 or 2 bits.

3 Design and Implementation of UART16550

3.1 CPU interface module

The CPU interface module completes the functions of interpreting CPU instructions, register configuration, and UART status reading. Through the 3-bit address line and 8-bit data line, the CPU can pre-set the baud rate of the baud rate generator so that the devices at both ends of the serial port can complete the receiving and sending work at the same baud rate. At the same time, the CPU interface receives the 5∽8-bit data that needs to be sent from the CPU and sends it to the sending module, or sends the data received by the receiving module to the CPU through the interface for data processing. In this interface module, 8 control and status registers are set, including RBR (Receiver Buffer Register) receiving buffer register, THR (Transmit Hold Register) transmission hold register, IER (Interrupt Enable Register) interrupt enable register, IIR (Interrupt ID Register) interrupt register, LCR (Line Control Register) line control register, LSR (Line Status Register) line status register, SCR (Scratchpad Register) temporary register and FCR (FIFO Control Register). Before using UART16550, the CPU must configure the control register, including baud rate, data bit number, parity check, stop bit number and FIFO control. This is also the programmable feature of 16550 that distinguishes it from general UART.

3.2 Baud Rate Generator

The baud rate is the number of bits of binary data transmitted per unit time, expressed in bits per second (b/s), also known as the data bit rate.

Relationship between receive/transmit clock frequency and baud rate:

Receive/transmit clock frequency = N × baud rate

N can be 8, 16, 32, and 64. In order to balance speed and stability, it is generally set to 16. N is set during hardware design and cannot be changed by software. The baud rate generator is composed of two 8-bit data registers combined into a 16-bit frequency division register, which can achieve 1 to 2 (16) division of the system frequency to achieve the predetermined baud rate setting.

3.3 FIFO Controller and Transmit/Receive FIFO

The cache is a prominent feature of 16550 and higher-end UARTs. 16550 has an 8-bit wide and 16-byte deep asynchronous FIFO. The FIFO controller reads information from the CPU interface, configures the transmit/receive FIFO, enables the FIFO when needed, and sends the real-time status of the FIFO to the CPU through the CPU interface to facilitate the CPU to read data. When the transmit FIFO is empty and the receive FIFO is full, the FIFO controller immediately generates an interrupt request to notify the CPU to proceed to the next step. In addition, when the DMA mode is configured, the CPU can send and read large amounts of data, which reduces the burden on the CPU and improves the operating efficiency of the entire system.

3.4 Sending module

The core of the sending module is the one hot coded state machine. It can read data from the FIFO, add a start bit, 1, 1.5 or 2 stop bits and a parity bit according to the information in the configuration register, and then send the packaged data to the serial receiving device through the shift register in a standard serial port protocol. As long as there is data in the send FIFO, the sending module will continue to send until the FIFO is empty. If the FIFO is not selected, the sending module directly receives data from the THR (Transmit Hold Register) send hold register and sends it directly without buffering.

3.5 Receiving module

The receiving module is the reverse execution of the sending module. It receives serial data from the outside, removes the start bit, stop bit and parity bit of the data according to the configuration, and generates an error message immediately if a data error occurs. If there is no error, the remaining 8 bits of useful data are sent to the receiving FIFO for the CPU to read. Similarly, the receiving module can also choose not to use FIFO. In this case, the receiving module will directly send the 8-bit data to the RBR (Receive Buffer Register) receiving buffer register, and then the RBR will send it to the CPU.

4. Verification of simulation results

The design is written in VHDL language on the FPGA Advantage platform, compiled and simulated by Modelsim, and downloaded to the circuit board through ISE for verification. The hardware verification FPGA chip uses Xilinx's Spartan3. XC400PQ208. Since a processor is required to verify the UART receive/send timing, the Xilinx MicroBlaze soft core is embedded in the FPGA to simulate the CPU control timing, and the communication with the computer serial port is realized through the FPGA external serial port. The timing simulation results using Modelsim are shown in Figure 3.

5 Conclusion

This article introduces the implementation of UARTl6550 on the programmable logic device FPGA, and verifies the design function through the actual circuit. The use of FP-GA can not only facilitate serial communication with the PC using the serial port protocol, but also expand the interface function of the board-level system. When applied inside the programmable device FPGA, it can greatly reduce the area of ​​the circuit board and improve the stability and programmability of the system.