Detailed explanation of the benefits of the Vivado Design Suite

After four years of development and one year of trial version testing, Xilinx's programmable disruptor, the Vivado Design Suite, has finally made its debut and has begun to be launched to customers through its early access program. The new tool suite is carefully built for the next decade of "all-programmable" devices and is committed to accelerating their design productivity.

"Over the past few years, Xilinx has pushed semiconductor technology innovation to a new level and unleashed the full system-level capabilities of programmable devices," said Steve Glaser, senior vice president of marketing and corporate strategy at Xilinx. "With the deployment of our award-winning Zynq™-7000 EPP (Extensible Processing Platform) devices, the revolutionary 3D Virtex®-7 Stacked Silicon Interconnect (SSI) technology devices, in addition to our continued innovation in FPGA technology, we are ushering in an exciting new era - the era of 'All-Programmable' devices."

"All-Programmable" devices will enable design teams to not only program custom logic for their designs, but also program based on ARM® and Xilinx processing subsystems, algorithms and I/O. In short, this is a comprehensive system-level device. Steve Glaser said, "Future "All-Programmable" devices will be more than programmable logic design. They will be programmable system integration, with fewer and fewer chips and more and more integrated system functions."

Steve Glaser also said that when creating systems using "All-Programmable" devices, designers are faced with a new set of integration and bottleneck problems in achieving design productivity. On the one hand, from the perspective of integration, this includes integrating algorithmic C and register transfer level (RTL) IP; mixing DSP, embedded, connection and logic domains; verifying modules and "systems", as well as reuse of design and IP. Implementation bottlenecks include chip planning and layering; multi-domain and large-scale physical optimization; multiple "design" and "timing" convergence; and the chain effect of later ECO and design changes.

It is precisely to solve the bottleneck of integration and implementation and enable users to fully utilize the system integration capabilities of these "All-Programmable" devices that Xilinx has created the new Vivado design suite.

Xilinx has used industry standards and advanced EDA techniques and methodologies in developing the Vivado Design Suite, a system-centric tool suite. As a result, customers who require a highly automated push-button flow or a very hands-on, modifiable flow can now design faster and more efficiently than ever before, even for Xilinx's largest FPGA designs, while working in a familiar and intuitive advanced EDA environment.

Xilinx developed the Vivado Design Suite to provide customers with a new tool suite with full system programmability capabilities that goes far beyond Xilinx's long-standing flagship ISE Design Suite. To help customers transition to the Vivado Design Suite, Xilinx will continue to firmly support ISE for customers using 7 series and earlier Xilinx FPGA technology. In the future, the Vivado Design Suite will become Xilinx's flagship design environment, supporting all 7 series devices and future Xilinx devices.

Tom Feist, senior director of design methodology marketing at Xilinx, predicts that once customers start using the Vivado Design Suite, they will immediately see its advantages over ISE.

Feist said: "Compared with similar competing tools, the Vivado Design Suite can reduce runtime by up to 4 times, which can significantly improve users' design productivity. At the same time, the design suite skillfully uses a variety of industry standards, such as System Verilog, SDC (Synopsys Design Constraints), C/C++/System C, ARM AMBA AXI-4 interconnect, and interactive TCL (Tool Command Language) scripts. Other outstanding advantages of the Vivado Design Suite include comprehensive cross-probing capabilities for Vivado's many reports and design views, advanced graphical IP integration capabilities expected to be launched in 2012, and the first commercial high-level synthesis technology (C++ to HDL synthesis) fully supported by FPGA manufacturers.

A design tool for next-generation programmable designs

Xilinx introduced the ISE Design Suite as early as 1997. The ISE Suite uses a very innovative timing-based place-and-route engine, which was acquired by Xilinx in April 1995 when it acquired NeoCAD. In the following 15 years, as FPGAs were able to perform increasingly complex functions, Xilinx added many new technologies to the ISE Suite, including multi-language synthesis and simulation, IP integration, and many editing and testing utilities, striving to continuously improve the ISE Design Suite from all aspects. Feist said that Xilinx created this disruptive new Vivado Design Suite by drawing on all the experience, precautions and key technologies of the ISE Design Suite and making full use of the latest EDA algorithms, tools and technologies.

“The Vivado Design Suite will significantly improve productivity for today’s designs and scale easily to address the capacity and design complexity challenges of 20nm chips and smaller process technologies,” said Feist. “EDA technology has come a long way in the past 15 years. We built this tool suite from the ground up so we can use the most advanced EDA technologies and standards in the suite, making it future-proof.”

Deterministic design convergence

The core of any FPGA vendor's integrated design suite is the physical design flow, including synthesis, floorplanning, placement, routing, power and timing analysis, optimization, and ECO. With Vivado, Xilinx has created a state-of-the-art design implementation flow that allows customers to reach design closure faster.

Extensible data model architecture

To reduce iterations and overall design time, and to improve overall productivity, Xilinx built its design implementation flow with a single, shared, scalable data model, a framework also commonly found in today's most advanced ASIC design environments. "This shared, scalable data model allows all steps in the flow, including synthesis, simulation, floorplanning, and place-and-route, to run on an in-memory data model, so debugging and analysis can be performed at every step in the flow, so that users can understand key design metrics such as timing, power, resource utilization, and routing congestion as early as possible in the design flow. And the estimates of these metrics will become more accurate as the design flow progresses during implementation," said Feist.

Specifically, this unified data model enables Xilinx to tightly integrate its new multi-dimensional analysis placement and routing engine with the suite's RTL synthesis engine, new multi-language simulation engine, and IP Integrator, Pin Editor, Floor Planner, Chip Editor, etc. In addition, the data model enables Xilinx to equip the tool suite with comprehensive cross-probing capabilities, allowing users to trace and cross-probe to a given problem in the schematic, timing report, logic cell or other views, all the way to the HDL code.

“You can now analyze every step of the design flow, and each step is linked to the next,” Feist said. “We also provide timing, power, noise and resource utilization analysis in the post-synthesis flow. So if I see that timing or power is not meeting requirements very early on, I can proactively address the problem with short iterations, rather than having to wait until place and route is complete and perform multiple long iterations to resolve it.”

Feist noted that the tight integration provided by this extensible data model also enhances push-button flows, which meet users’ expectations for tools that automate most of the work. Feist said this model also meets customers’ needs for more advanced control, deeper analysis, and control over the progress of each design step.

Feist said that Vivado provides users with the function of design

partitioning, which can handle the design of synthesis, execution and verification separately, so that different teams can be set up to design separately when executing large projects. At the same time, the new design preservation function can realize the reuse of timing results and the partial reconfiguration of the design.

Vivado also includes a new synthesis engine designed to handle millions of logic cells. The key to the new synthesis engine is its strong support for System Verilog. "Vivado's synthesis engine supports the synthesizable subset of the System Veriog language better than any other tool on the market," said Feist. Its synthesis speed is three times that of Xilinx's ISE Design Suite synthesis tool XST, and supports a "fast" mode that allows designers to quickly grasp the area and size of the design. In addition, it also allows them to debug problems 15 times faster than before using RTL or gate-level schematics. As more and more ASIC designers turn to programmable platforms, Xilinx has also promoted Synopsys Design Constraints (SDC) throughout the Vivado design flow. The use of standards opens a new level of automation, and customers can now access advanced EDA tools to generate constraints, check cross-clock domains, formal verification, and even static timing analysis using tools like Synopsys PrimeTime. [page]

Multi-dimensional analysis layout

Feist explained that previous generation FPGA design suites used a one-dimensional timing-based place-and-route engine that used simulated annealing to randomly determine where the tool should place logic cells. With these tools, the user enters the timing, and the simulated annealing algorithm starts with a random initial placement seed based on the timing, and then moves cells locally to "try" to match the timing requirements. "This approach was feasible at the time because the design size was very small and logic cells were the main cause of delay. But today, with the increasing complexity of designs and the advancement of chip processes, interconnects and design congestion have become the main causes of delay. Place-and-route engines using simulated annealing algorithms are fully capable for FPGAs with less than 1 million gates, but designs above this level are overwhelmed. Not only is there congestion, but as the size of the design exceeds 1 million gates, the results of the design begin to become more unpredictable."

With an eye toward the future, Xilinx developed a new multi-dimensional analysis placement engine for the Vivado Design Suite that rivals the engines used in today’s million-dollar ASIC place-and-route tools. The new engine analyzes to find solutions that radically minimize the three dimensions of a design: timing, congestion, and wire length. “The Vivado Design Suite’s algorithms optimize globally for optimal timing, congestion, and wire length simultaneously, taking into account the entire design, rather than the local adjustments that simulated annealing algorithms make,” said Feist. “This allows the tool to quickly and deterministically place and route tens of millions of gates while maintaining a consistently high quality of results (see Figure 1). And because it handles all three elements simultaneously, it also means fewer reruns of the process.” Figure 1: The Vivado Design Suite completes designs of all sizes faster and with better quality than other FPGA tools

To demonstrate this advantage, Xilinx used a push-button flow to run the original RTL developed for the Xilinx Zynq-7000 EPP simulation platform in both the ISE Design Suite and the Vivado Design Suite, while targeting each tool to the world’s largest FPGA device, the Virtex-7 2000T FPGA with stacked silicon interconnect technology. The Vivado Design Suite’s place-and-route engine completed the placement of 1.2 million logic cells in just five hours, while the ISE Design Suite took as long as 13 hours (Figure 2). The design implemented with the Vivado Design Suite also had significantly less congestion (shown in gray and yellow in the design) and a smaller device footprint, which indicates shorter overall trace lengths. The Vivado Design Suite implementation also demonstrated better memory compilation efficiency, using only 9GB to achieve the design’s required memory, while the ISE Design Suite used 16GB.

“Essentially, what you’re seeing is that the Vivado Design Suite can implement the entire design using only three-quarters of the device resources while meeting all the constraints,” said Feist. “This means that users can add more logic and on-chip memory to their designs, and even use smaller devices.” Figure 2: The Vivado Design Suite’s multidimensional analysis algorithms create layouts optimized for best timing, congestion, and trace lengths, not just best timing.

Power optimization and analysis

In today's era, power consumption is one of the most critical aspects of FPGA design. Therefore, the focus of the Vivado design suite is to focus on using advanced power optimization technology to provide users with greater power reduction advantages in their designs. "We have adopted the advanced clock gate control technology currently seen in ASIC tool suites, which can have the function of design logic analysis while eliminating unnecessary flips," said Feist. "Specifically, the new technology focuses on the flip factor 'alpha', which can reduce dynamic power consumption by 30%." Feist said that Xilinx began to apply this technology in the ISE design suite last year and has been using it ever since. Vivado will continue to strengthen the application of this technology.

In addition, with this new scalable data sharing model, users can get power consumption estimates at every stage of the design process, so that they can analyze problems in advance and solve them in the design process. [page]

Simplify Engineering Change Orders (ECOs)

Incremental flows make it possible to quickly process small design changes, reimplementing only a small part of the design after each change, making iterations faster. They also enable faster performance after each incremental change, eliminating the need for multiple design iterations. To this end, the Vivado Design Suite also includes a new extension to a popular ISE FPGA Editor tool called the Vivado Device Editor. Feist said that using the Vivado Device Editor on a place-and-route design, designers now have the ability to do engineering change orders (ECOs) to move cells, rewire, connect a register output as a debug pin, and modify the parameters of a DCM or look-up table (LUT) - late in the design cycle without having to go back to the design for resynthesis and reimplementation. He said that no other FPGA design environment in the industry currently offers this level of flexibility.

Built on industry standards

Four and a half years ago, when Xilinx started to build the Vivado Design Suite from scratch, the first task of the architecture was to replace the proprietary format with a standard design environment. It is committed to creating an open environment that allows customers to expand with EDA tools and third-party IP. For example, the Vivado Design Suite supports SDC (Synopsys Design Constraints), ARM AMBA AXI 4 IP interconnect standards, IP-XACT IP packaging and delivery standards, and provides powerful interactive TCL scripting capabilities in the new environment.

Process automation, non-process mandatory

In building the Vivado Design Suite, the Xilinx tool team followed the principle of "automating the way you design, not forcing the way you design." "Whether users start programming in C, C++, SystemC, VHDL, Verilog, System Verilog, MATLAB or Simulink, and whether they use our IP or third-party IP, we provide a way to automate all processes and help customers improve productivity," said Feist. "We also take into account the various skill levels and preferences of our users, including those who need a full push-button flow, those who perform analysis at every step of the design process, and even those who think that using a GUI is a novice and prefer to complete the entire design process in TCL in command line or batch mode. Users can choose the suite features based on their specific needs."

To further enhance the design experience for all users, Xilinx has added some fantastic new capabilities to the Vivado Design Suite and has also added Chip Editor capabilities to its customer-acclaimed FPGA Editor.

IP Packagers, Integrators and Catalogs

Xilinx's tool architecture team focused on the design of IP functions specifically for the new suite to facilitate IP development, integration and archiving. To this end, Xilinx developed three new IP functions: IP packager, IP integrator and scalable IP catalog.

“It’s hard to find an IC design today that doesn’t use IP,” said Feist. “Our adoption of industry standards and the provision of tools specifically designed to facilitate IP development, integration and archiving/maintenance help IP vendors and customers in our ecosystem partners quickly build IP and increase design productivity. More than 20 vendors are already offering IP that supports this latest suite.”

With IP Packager, Xilinx customers, Xilinx's own IP developers, and Xilinx ecosystem partners can convert part of their design or the entire design into a reusable core at any stage of the design flow, whether it is RTL, netlist, laid-out netlist, or even a post-placement netlist. IP Packager creates an IP-XACT description of the IP so that users can easily integrate the IP into future designs using the new IP Integrator. IP Packager sets the data for each IP in an XML file. Feist said that once the IP is packaged, the IP can be integrated into the rest of the design using the IP Integrator feature.

“IP Integrator allows customers to integrate IP into their designs at the interconnect level rather than at the pin level,” Feist said. “You can drag and drop IPs onto your canvas one by one, and IP Integrator will automatically check in advance whether the corresponding interfaces are compatible. If they are compatible, you can draw a line between the cores, and the integrator will automatically write the detailed RTL to connect all the pins.”

“The key here is that you can take the output of four or five modules that have been integrated with IP integrator and repackage it with a packager,” Feist said. “This becomes an IP that others can reuse. This IP does not necessarily have to be RTL, it can be a netlist after placement, or even a netlist module after place and route. This can further save integration and verification time.”

The third major feature is the scalable IP catalog, which enables users to create their own standard IP library with IP they create themselves and IP licensed by Xilinx and third-party vendors. The catalog created by Xilinx in accordance with the IP-XACT standard allows design teams and even enterprises to better organize their IP for sharing throughout the organization. Feist said that Xilinx System Generator and IP Integrator have been integrated with the Vivado scalable IP catalog, so users can easily access cataloged IP and integrate it into their design projects.

Ramine Roane, director of product marketing at Vivado, said: "Previously, third-party IP vendors delivered IP in different formats using Zip files. Now, they deliver IP in a unified format that is ready for immediate use and compatible with the Vivado suite." [page]

Vivado HLS brings ELS into the mainstream

Perhaps the most forward-looking of the many new technologies in the Vivado Design Suite is the new Vivado HLS (High-Level Synthesis) technology, which Xilinx acquired when it acquired AutoESL in 2010. Before acquiring this best-in-class technology, Xilinx conducted an extensive evaluation of commercial ESL solutions. The results of a study by market research firm BDTI helped Xilinx make the acquisition decision (see Xilinx China Newsletter No. 36, "BDTI Study Certifies High-Level Synthesis Flow for DSP-Based FPGA Design" http://china.xilinx.com/china/xcell/xl36/2-7.pdf).

Feist said: "Vivado HLS has comprehensive coverage of C, C++, SystemC, and is capable of floating-point operations and arbitrary-precision floating-point operations. This means that if users wish, they can use the tool in an algorithm development environment rather than a typical hardware development environment. The advantage of this is that algorithms developed at this level can be verified orders of magnitude faster than at the RTL level. This means that algorithms can be accelerated while exploring the feasibility of algorithms, and trade-offs between throughput, latency and power consumption can be achieved at the architectural level."

Designers can use the Vivado HLS tool to perform various functions in various ways. To demonstrate, Feist explained how users can develop IP with Vivado HLS and integrate it into their designs through a common flow.

In this flow, the user first creates a C, C++, or SystemC representation of the design, and a C test bench that describes the expected design behavior. The system behavior of the design is then verified using the GCC/G++ or Visual C++ simulator. Once the behavioral design is running well and the corresponding test bench issues are resolved, the design can be run through Vivado HLS Synthesis to generate an RTL design, which can be either Verilog or VHDL. Once you have the RTL, you can then perform a Verilog or VHDL simulation of the design, or create a SystemC version using the tool's C wrapper technology. You can then perform a System C architectural-level simulation to further verify the architectural behavior and functionality of the design based on the previously created C test bench.

Once the design is solidified, it can be run through the physical implementation flow of the Vivado Design Suite, programmed onto a device, run in hardware and/or converted into reusable IP using IP Packager. The IP can then be integrated into the design using IP Integrator or run in System Generator. Figure 3 – Vivado HLS enables design teams to start their design directly at the system level.

This is just one way to use the tool. In fact, in an upcoming issue of Xilinx Xcell Magazine, Agilent's Nathan Jachimiec and Xilinx's Fernando Marinez Vallina will describe how they used Vivado HLS technology (called AutoESL technology in the ISE Design Suite flow) to develop a UDP packet engine for Agilent.

VIVADO Simulator

In addition to Vivado HLS, the company has also developed a new mixed-language simulator for the suite that supports both Verilog and VHDL. Feist said that with just a click of the mouse, users can start behavioral simulation and then view the results from the integrated waveform viewer. By using the latest performance-optimized simulation kernel, behavioral-level simulation speed can be accelerated, and the execution speed is three times faster than the Silinx ISE Design Suite simulator. With hardware co-simulation, gate-level simulation speed can be accelerated by 100 times.

2012 Supply

Previously, Xilinx ISE Design Suite released four versions for different types of designers (logic, embedded, DSP and system). Xilinx will launch two versions of Vivado Design Suite. Among them, Vivado Basic Design Edition includes new IP tools and Vivado's synthesis-bitstream flow. And Vivado System Edition includes all tools of Design Edition, System Generator and Xilinx's latest Vivado HLS tool.

Vivado Design Suite 2012.1 is now available in the early access program. For more details, please contact your local Xilinx representative. 2012.2 will be publicly available in the middle of the second quarter, and WebPACK will be available later this year. Current ISE Design Suite users who have not yet expired support will receive the new Vivado Design Suite in addition to ISE at no charge.

Xilinx will continue to support the ISE Design Suite for users of devices prior to 28nm. For more information on Vivado, visit www.xilinx.com/design-tools.