Application of sound effect chip CS4235 in DSP embedded systems

　　 introduction 　　

　　Sound card technology is one of the key technologies of multimedia computer technology.

　　Its emergence makes computers more expressive. At present, due to the simple structure and low sampling rate of the sound recording and playback chips used, the sound quality in embedded systems is relatively poor, which is far from meeting people's requirements for embedded systems for high-end life and learning. If sound card technology can be applied to embedded systems, the sound quality of the entire system will surely rise to a new level due to the powerful functions of the sound card. Through analysis, WSS (Windows Sound System) is compatible with the interface principle of the sound card and PC ISA bus, and we applied the sound effect chip CS4235 to the DSP-based embedded system. The reason for not using a ready-made sound card and using the sound effect chip on it is because the design is more flexible and convenient, and corresponding functions can be added or deleted according to system needs; the reason why the MCS51 series is not used and the DSP is used is because operating the sound card requires too many system resources. MCS51 It does not have this capability, otherwise the hardware interface circuit will be quite complicated.

　　1 CS4235 principle and structure

　　1.1 How the sound card works 　　

　　Figure 1 shows the basic working principle of the sound card: the host sends the digitized sound signal to the digital-to-analog converter (D/A) in the form of PCM through the bus, converting the digital signal into an analog audio signal; at the same time, it can The A/D converter converts the input signal from the microphone or CD into a digital signal and sends it to the computer for various processing.

　　1.2 CS4235 functional structure 　　

　　WSS is an audio subsystem standard defined by multimedia extensions in the Windows environment proposed by Microsoft to unify the standard for sound cards and ultimately provide convenience for applications, including hardware platforms and software interfaces [1]. CS4235 is a sound card core chip that is adapted to WSS and provides an ISA bus interface. In addition to sound collection and playback, all other controls rely on the host; it takes up more host time, but the cost is relatively low. The functional block diagram of CS4235 is shown in Figure 2. As can be seen from Figure 2, CS4235 is a complete audio subsystem integrated circuit that provides 16-bit stereo ADC and DAC, on-chip reconfigurable digital filters, analog and digital mixers with programmable gain values ​​and attenuation values. , optional serial interface, full-duplex channel with simultaneous recording and playback capabilities. The documentation for CS4235 can be found in reference [2]. 　　

　　Due to space limitations, the analog hardware part of CS4235 is not introduced here, but the digital hardware interface between CS4235 and DSP is mainly studied. Because TMS320F206 (referred to as F206) is a low-price, high-performance 16-bit fixed-point arithmetic digital signal processor (DSP) with extremely high cost performance, it has become an ideal substitute for high-end microcontrollers in communications, voice processing, military, and instrumentation. It has been widely used in instrumentation, image processing and other fields [3], so F206 is selected as the DSP in the system. The 8-bit parallel interface provided by CS4235 is compatible with the ISA bus. Is it also compatible with the external expansion bus of the DSP? Table 1 lists the signal pins and brief descriptions of the CS4235 and ISA bus interface, and the corresponding pins of F206 are also listed accordingly. As can be seen from Table 1, in order to realize the direct operation of CS4235 by DSP, the DSP system must provide the above-mentioned ISA bus signal. DSP chips generally provide data signal lines, address signal lines, I/O read and write signal lines and READY signal lines, and also have multiple interrupt input pins; but do not directly have DMA function pins, which creates a problem for DSP and CS4235 The interface between them brings inconvenience, which is the main problem to be solved in this article. Table 1 Signal pins of CS4235 and ISA bus interface Simple description of signal pins DSP (F206) corresponding pins SD<7:0> Bidirectional system data bus D<7:0> SA<11:0> System address bus A< 11:0> IOR I/O read command is decoded by IS and RD to get IQW=IS+WR IOW I/O write command without AEN address enable signal READY IOCHRDY I/O channel ready INT2 (in practical applications, only Select 1 interrupt line to connect to DSP) IRQInterrupt request signal: IRQA=IRQ5, IRQB=IRQ7 IRQC=IRQ9, IRQC=IRQ11, IRQD=IRQ11 IRQE=IRQ12, IRQF=IRQ15, IRQG=IRQ10 No DRQDMA application signal: DRQA=DRQ0 DRQB=DRQ1 DRQC=DRQ3 No DACKDMA response signal: DACKA=DACK0 DACK1=DAC, DACKC=DACK3 RS RESET sound card reset signal　

　　2 Hardware interface between DSP and CS4235

　　2.1 F206 uses direct memory access of HOLD operation 　　

　　The key to F206's DMA function is that this type of chip provides two signal pins: HOLD/INT1 and HOLD. The HOLD operation process controlled by these two signals is as follows.

 ①. An external device can drive this pin low to request control of the external bus. If the HOLD/INT1 interrupt line is enabled, then this will trigger an interrupt. ② When responding to an interrupt, software logic can cause the processor to send a response signal, indicating that it will give up control of its external bus. According to the external address signal (A15"A0), data signal (D15"D0) and memory control signal () are set to a high impedance state. 　　

　　As can be seen from ① and ②, the HOLD operation of F206 allows direct memory access to external programs, data and I/O space, but this function is implemented in the INT1 interrupt program, so the interrupt line INT1 has a negative impact on the falling edge and rising edge. Both should be sensitive. When F206 detects a falling edge, it completes the current instruction being executed and then forces program control to go to the interrupt service subroutine, which executes the IDLE (idle) instruction. According to IDLE, becomes active and the external bus is placed in a high-impedance state. Only after detecting the rising edge on the HOLD/INT1 pin does the CPU exit the IDLE state, become inactive, and return the external bus to the normal state. 　　

　　From the above analysis, we can see the difference between the DMA operation of F206 and the DMA operation of PC. In the PC, after the CPU receives the DMA request signal, it forces the CPU to put its address, data and some control pins in three states after the current bus cycle ends, thus giving up control of the bus and giving a DMA response signal; after the DMA operation is completed and the DMA request signal is invalid, the CPU resumes control of the system bus. In C2XX, the DMA application signal will cause the F206 interrupt. A software instruction is issued in the interrupt program to make each signal pin of F206 in three states, and a DMA response signal is also given; after the DMA operation is completed, but F206 detects After the DMA request signal is invalid, although the bus returns to the normal state, F206 is still in the interrupt program. From the above analysis, it can be seen that although interrupts need to protect breakpoints and scenes, the DMA processing speed of F206 is much lower than that of PC. After all, F206 also implements DMA operations, so that the sound card can be controlled with the help of DMA controller 8237. DMA operation access. 2.2 Interface circuit between DSP and DMA controller 8237 　　

　　8237 is a high-performance programmable DMA controller chip that can be easily connected to the CPU to achieve direct data exchange between external devices and memory. Its internal structure and pin signals can be found in literature [4]. The controller can be programmed to provide a variety of control features to optimize system performance and increase data throughput, with a maximum data transfer rate of up to 1.6 MB/s. Figure 3 shows the main circuit of the interface between F206 and 8237. The DMA request signal HRQ sent by 8237 to the DSP to control the bus is decoded by GAL16V8 and sent to the HOLD/INT1 pin of the DSP; similarly,

　　 The DMA response signal of the DSP is also decoded by GAL16V8 and sent back to the HLDA pin of the 8237. The function of the address latch 74LS573 is to latch the high 8-bit address A8"15 output by the 8237 through the data line D0"7 during the DMA service cycle. Since DSP does not directly provide ,, and signals, these signals can only be decoded by GAL16V8. 　　

　　The circuit shown in Figure 3 provides 4 channels of peripheral request DMA service signals, and the 8237 directly has the AEN pin, which meets all the requirements in Table 1, so that the interface between the DSP and the sound card can be correctly realized. In actual work, we set DREQ1 and DACK1 of 8237 as the playback channels of the sound card according to the usage of the sound card in the PC. DREQ3 and DACK3 of 8237 are the collection channels of the sound card. The interrupt request signal IRQ7 of the sound card is reversed with the DSP after being reversed by GAL16V8. pin connections. 2.3 System working principle and timing 　　

　　The DMA operation process of the sound card by the DSP system shown in Figure 3 can be described in Figure 4, and the working sequence is shown in Figure 5. The working principle and operation sequence of the system are described as follows with reference to Figure 4 and Figure 5: ① CS4235 sends the DMA request signal DREQ to the DMA controller 8237; ② 8237 sends the bus request signal HRQ to the DSP; ③ The DSP pin detects the falling edge. After that, enter the INT1 interrupt, after protecting the breakpoint and the scene, send the IDLE instruction, the pin level of the DSP becomes low, and respond to the external DMA request; ④ After 8237 takes over the bus, it first sends the response signal DACK to the DMA request to CS4235, indicating that Allow CS4235 to perform DMA transmission, and then send the address and read and write commands sequentially according to the preset initial address and the number of bytes to be transmitted, so that data can be directly exchanged between RAM CS4235 until all data exchange is completed;

　　⑤After the DMA transfer is completed, the bus request signal HRQ to the CPU is automatically cancelled. At this time, the DSP detects the rising edge of the pin, and the DSP returns to the next instruction of the IDLE instruction. The DSP obtains control of the bus and continues to execute the program in INT1.

　　3 Software interface between DSP and CS4235 　　

　　The ISA bus interface of CS4235 is plug-and-play (PnP). The sound card must be activated through programming before it can directly access the sound card registers and configure the sound card to complete different tasks. In fact, the ISA slot designed for old non-PnP ISA cards is also suitable for PnP cards, and only requires corresponding changes in the software. The recognition process of PnP cards by DSP is exactly the same as the recognition process of PnP cards by microcomputer. Figure 6 shows the program flow of recognition of PnP cards by DSP. From the above identification and configuration process of PnP card, it can be seen that if it is in a PC environment, then this process can be completed automatically; but in a system designed by the user, this process seems a bit cumbersome and not very meaningful. . Is it possible to program each PnP card directly, bypassing the PnP protocol, just like the old ISA cards? In fact, most chips do provide this concise and fast method, collectively called the "XX company keyword" interface method. This article uses CS4235 as an example to introduce this interface technology. After completing the 5 steps given below, the sound card will operate the same as the old ISA sound card. The only drawback is that this method will not work if two sound cards of this type are used in the system. ① The DSP sends the 32-byte "Crystal Key" to the address port 279H, and the PnP card immediately enters the configuration state. These 32 bytes of data are: 96, 35, 9A, CD, E6, F3, 79, BC, 5E, AF, 57, 2B, 15, 8A, C5, E2; F1, F8, 7C, 3E, 9F, 4F , 27, 13, 09, 84, 42, A1, D0, 68, 34, 1A. ② DSP sends the handle number to 279H.

③ DSP directly configures the configuration register of each logical device and sets the I/O port base address, interrupt number and DMA channel selection. ④ DSP sends 79H to 279H to activate CS4235. ⑤ DSP prohibits the PnP card from participating in future PnP cycles. 　　

　　After the above configuration is completed, CS4235 automatically exits the configuration state and enters normal operation, so that the registers of CS4235 can be directly programmed according to specific functional requirements.

　　Conclusion 　　

　　In the fully digital language learning system, we use the sound effect chip CS4235 to replace the previously used voice recording and playback chip MSM6588. Although the hardware circuit design and software operation are much more complicated, the important indicators of the language learning system, such as passband, signal-to-noise ratio and distortion, have reached the sound quality standards of multimedia computers. Practice has shown that many key technologies and excellent design ideas in microcomputers can be transplanted into embedded systems, making embedded systems more colorful.