The principle and application of MAP-CA wideband digital signal processor

　　As a major supplier of integrated broadband digital communications and media processor core equipment in the consumer electronics equipment market, Equator Technology has launched a high-speed broadband digital signal processor MAP-CABSP, operating at a clock cycle speed of 300MHz , its processing capability is 30 GOPS (30 billion integer operations per second), and its processing speed is equivalent to 6.4 times that of Pentium III and more than 10 times that of other solutions. Its core functionality is designed through software for broadband applications with high performance, large video streams. Programmable chips allow service providers to deploy more services and functions, such as time-shifting, secure media playback and targeted advertising. It has broad application prospects in high-performance broadband application products such as set-top boxes, digital TVs, video conferencing systems, medical imaging products, digital video editing systems and office automation. MAP-CA is one of Equator's MAP series of very long instruction word processors.

　　1 System block diagram

　　The internal block diagram of the MAP-CA wideband signal processor (BSP) is shown in Figure 1. It mainly includes a very long instruction word processor core (The VLIW core), a programmable bit stream coprocessor (The VLx), video filter coprocessor, display refresh controller and rich digital I/O interfaces. MAP-CA supports various software-implemented compression and decompression of videos, images, and signals. This software-implemented algorithm has great advantages over hardware implementation and is very convenient to upgrade.

　　2 Hardware interface

　　MAP-CA's hardware interfaces include video input and output interfaces, audio input and output interfaces, PCI bus interfaces, SDRAM interfaces, display controller interfaces, I2C interfaces, ROM controller interfaces and standard online programmable JTAG interfaces.

　　2.1 Video input and output interface

　　MAP-CA has two video input ports and one video output port. Each input port supports MPEG-2 Transport Channel Interface (TCI) or ITU-RBT.601/656 signal format. The output port supports ITU-R BT.601/656 compatible signals. What's even more amazing is that these video input and output ports can also be used as general data transmission ports. In TCI interface mode, the video input interface can input MPEG-2 video data packets in serial or parallel mode. By default, serial data is input at tci_data[0], and parallel data is input at tci_data[7:0]. The TCI interface can intelligently determine the synchronization bit in the input data packet, or use the external tci_cync signal to synchronize the input data. Once the synchronization signal is detected, MAP-CA will send the data to the on-chip memory. For the input signal of ITU-RB RT.601/656, you only need to connect another external video encoder (such as the SAA7111A chip of Philips Company) to convert the NTSC/PAL signal into the ITU-R BT.656 signal and decode it. The device can also be controlled using the I2C bus that comes with the system. The video input and output interface supports separate H/V synchronization (ITU-R BT.601) or embedded synchronization signal (ITU-R BT.656) signals, which can seamlessly interface with NTSC/PAL video encoders. You can also use the system's own I2C bus of ITU-R BT.656 to control the NTSC/PAL video encoder. When used as a general data transmission port (GPDP), it can perform parallel input and output of 8-bit data like an ordinary data port. Coupled with a clock and a pair of handshake signals, this interface provides an alternative implementation of multiple MAP signal processor connections. The maximum data transfer rate supported by this data port can be up to 60Mbps.

　　2.2 Audio input and output interface

　　MAP-CA supports multiple audio interface formats. It has an IEC958 audio interface and an I2S interface. Among them, the IEC958 audio interface supports Sony and Philips digital interfaces S/PDIF, AES/EBU interface, and TOSLINK interface. The I2S interface is mainly used in high-quality audio D/A converters in home theaters. The I2S interface of MAP-CA complies with the standard serial protocol and can connect up to three stereo DACs and one DAC, supporting 48kHz, 44.1kHz and 32kHz. Audio sampling frequency. The interface also supports two working modes: master and slave.

　　2.3 PCI bus interface

　　MAP-CA's PCI bus interface is fully compatible with the PCI 2.1 specification, with a maximum data transfer rate of up to 66Mbps. The configuration register in the PCI interface is initialized by ROM when the chip is powered on. When the PCI interface of MAP-CA is used as the target device of the PCI bus, the SDRAM inside MAP-CA can be accessed through the PCI interface, and some control registers, PIO spaces, etc. that are relatively transparent to the programmer can also be accessed. As a PCI master, the PCI interface can use the very long instruction word core (VLIW core) and coprocessor to initialize PCI bus requests, and can also initiate memory, I/O and configuration commands. MAP-CA can act as a host on the PCI bus. It has three pairs of application/response signal lines, so that in multi-processor system applications, up to 4 MAP-CAs can be connected to the PCI bus at the same time without any intermediate switching device. MAP-CA is a single 3.3V power supply device. If used in a 5V PCI bus structure system, a 3.3V ~ 5V level conversion chip is required.

　　2.4 SDRAM interface

　　The SDRAM interface control unit allows users to connect up to 128MB of external SDRAM without any external logic. External PCI master devices can also access SDRAM through the address decoding unit of the PCI interface unit. The storage control interface also includes a programmable hardware unit that can realize data transfer and queuing operations from memory to memory and from memory to cache. The on-chip phase-locked loop generates the clock signal of the storage control unit, and uses this clock to synchronize MAP-CA and SDRAM, which greatly facilitates the matching of the CPU core with various memories of different speeds.

　　2.5 Display refresh controller interface

　　There are many high-end graphics display technologies in the display controller interface (Display Refresh Control, DRC). Complex video mixing, 2D image mixing, and navigation services are all well implemented in the display hardware interface. The interface also supports color space conversion and graphics gamma correction, and the output formats are YcbCr and RGB. The maximum resolution supported by DRC is 1280%26;#215;1024. When the clock frequency reaches 108MHz, 16-bit pixel format can be supported.

　　2.6 I2C interface unit

　　The I2C bus is a serial communication bus developed by Philips Company. It uses two bidirectional wires (data via SDA, clock line SCL) to achieve serial communication between devices (between IC and IC, referred to as I2C: integrated-circuit interface circuit). MAP-CA can serve as both a host on the I2C bus and a slave to exchange address data information with external I2C bus devices. Different from the general I2C interface, MAP-CA also has an additional selection output line iic_select, which can control the external multiplexing circuit or level converter through software, so that this interface can choose whether to be used as an I2C bus. This selection output line can also be used as a normal output line.

　　2.7 ROM controller interface

　　The ROM controller interface unit (ROMCON) has the following four different functions: %26;#183;As an interface for the configuration and startup circuit of MAP-CA, it reads the system configuration and starts the program when the system starts. %26;#183;As a FLASH ROM interface, it controls the read and write operations of off-chip FLASH ROM. %26;#183;As interrupt control and arbitration logic, it controls the enabling, setting and clearing of VLIW core and PCI bus interrupts generated by software and hardware. %26;#183;As an access interface to internal programmable registers, access to internal programmable registers can be achieved.

　　2.8 JTAG interface

　　MAP-CA supports the standard IEEE 1149.1 boundary scan test port, which can easily achieve online debugging. When the JTAG interface is not used, the TCK and TRST pins should be connected to ground.

　　3 Software development

　　MAP-CA can be programmed entirely in C and does not require any low-level languages. To this end, Equator Technology provides a software development kit called iMMediaTools, which includes an optimized parallel C language compiler, FIRtree media essence extended C language, assembler, connector, source code debugger, two virtual Library functions for machine simulators and classification. In order to facilitate the processing of video images, Equator Company provides a series of media library reference source code software packages for video processing, including commonly used MPEG-2 encoding and decoding modules, MPEG-4 encoding and decoding modules, H.268+ Encoding and decoding software modules and MPEG audio codec modules.

　　3.1 C compiler

　　The MAP-CA development system includes the iMedial C compiler with the FIRtree Media Essentials Extended C language. FIRtree is a specialized high-speed media processing extension language in the form of single instruction multiple data streams. This C compiler uses a large number of optimization and global configuration technologies, leaving the operations involving the hardware to the compiler to complete the conversion, so that programmers can fully utilize the full performance of the hardware without using time-consuming and laborious assembly language. Using C language programming can save development costs, speed up product development cycles, reduce system costs, reduce maintenance time, and is very convenient for software upgrades. The entire compiler uses a complex series of inline extensions, definitions, and frequency tracking algorithms to better achieve code efficiency. For programmers, they are still faced with a familiar integrated development environment. For programmers, they are still faced with a familiar integrated development environment (IDE). In this integrated development environment, source code can be programmed, inspected, tested, assembled and connected.

　　3.2 FIRtree media essential language

　　The FIRtree Media Essentials extension C language reads data from data memory 128-bit words at a time. This 128-bit word of data can include many 32-bit or 64-bit operands. It only requires two additional registers to store immediate data, and the instructions in these data units can be executed in parallel at the same time.

　　3.3 Library functions

　　The iMMediaTools software development kit provides a standard C language runtime library and a function library package that specifically supports the internal resources of the MAP-CA processor (data flow container and variable length encoding coprocessor, etc.).

　　4 Application examples

　　In an actual system, the MAP-CA wideband signal processor can have two main modes and non-main modes. In master mode, MAP-CA acts as the host on the system PCI bus, controlling peripheral devices to form an independent system. Non-main mode usually uses the entire application system as a universal PCI card of the PC. The PC host can run operating systems such as WINDOWS NT, WINDOWS 2000 or RED HAT LINUX. For the convenience of application, a common interface mode is given here, which is a non-main mode and can meet the needs of most systems. Use the MAP-CA wideband signal processor to design a video signal processing card. The schematic block diagram is shown in Figure 2. After the input analog video signal (S-Video or CVBS) undergoes analog-to-digital conversion and data format processing by the video encoder SAA7111A, the digital video stream in the standard ITU-R BT.656 format is obtained and sent to MAP-CA for processing, and is processed by Equator The company's powerful software support can realize various video operations, such as MPEG-2, MPEG-4 compression processing, etc. The video signal output in the ITU-R BT.656 format can be digital-to-analog conversion and format conversion through the Philips video encoder SAA7121, and turned into an S-VIDEO TV signal output in compliance with the international standard NTSC/PAL format. There is also an SVGA-compatible RGB output port that can be connected directly to a computer monitor. The audio input signal IIS input and output bus is connected to the external audio signal through the audio digital-to-analog converter CS4334 and the analog-to-digital converter CS5331A. In addition, the system is connected to an external 27MHz voltage-controlled crystal oscillator as a synchronization clock for audio and video encoding; a 4MB FLASH ROM memory is used as the system's startup circuit and non-volatile memory; and a 128MB PC133 SO-DIMM SDRAM memory is also connected as a Where system programs run and variables are stored.