Design of multifunctional signal generator based on FPGA LPM

Abstract: With FPGA chip as carrier, a multifunctional signal generator is designed through LPM_ROM module of QuartusII and VHDL language as core . According to the selection of input signal, it can output five kinds of signals, such as increasing sawtooth wave, decreasing sawtooth wave, triangle wave, step wave and square wave. The waveform simulation and timing analysis are carried out through QuartusII software. After the simulation is correct, the resources provided by the experimental board are used to download to the chip to realize the predetermined function.

Signal generator , also known as waveform generator , is a commonly used signal source , widely used in electronic circuits, communications, control and teaching experiments. It is one of the most important instruments in scientific research and engineering practice . In the past, it was mostly composed of hardware, with a complex system structure and poor maintainability and operability. With the development of computer technology, the design and production of signal generators are increasingly based on computer technology, with a wide variety of types and great differences in price and performance. It is implemented with FPGA or CPLD. Its advantages are that it can perform functional simulation, and the on-chip resources of FPGA and CPLD are rich, and the design process is simple. The system composed of FPGA is used to generate waveform signals. This system can be connected to the host system, display waveform signals with the corresponding upper-level software, and is convenient for program writing. It also has an A/D0809 interface that can generate analog signal output and connect to an external oscilloscope .

1 LPM Customization of Sine Signal Generator

The sine signal generator consists of a counter or address generator (6 bits), a sine signal data ROM (6-bit address lines, 8-bit data lines , containing 64 8-bit data, one cycle), a schematic top-level design and an 8-bit D/A ( DAC0832 is used instead in the experiment).

Its block diagram is shown in Figure 1. The signal generation module will generate various required signals. These signals can be generated in many ways, such as using a counter to directly generate signal output, or using a counter to generate the address of a memory , and storing the data of the signal output in the memory. The control module of the signal generator can be implemented with a data selector, and an 8-to-1 data selector can be used to select 5 signals.

Figure 1 Signal generator structure diagram

Finally, the waveform data is sent to the D/A converter to convert the digital signal into an analog signal for output. Using an oscilloscope to test the output of the D/A converter, 5 types of signal outputs can be observed.

1.1 Customize initialization data file

There are two formats of initialization data files in the LPM_ROM module that QuartusII can accept: .mif format file and .hex format file. In actual applications, you only need to use one of the formats. The following uses the .mif format file to call out the selection window for generating the ROM data file size. According to the 64-point 8-bit sine data, the optional ROM data number Number is 64, and the data width Word size is 8 bits. Click the OK button , and the empty .mif data table shown in Figure 2 will appear. The data format in the table can be selected by right -clicking the address data on the edge of the window.

Figure 2.mif data table

Fill the waveform data into the mif file table. You can also use editors other than QuartusII to design the MIF file. The format is as follows:

#include < ST dio.h>

#include "math.h"

main()

{int i; float s;

for (i=0; i<1024; i++)

{ s = sin(atan(1)*8*i/1024);

printf("%d : %d;\n",i,(int)((s+1)*1023/2)); }}

After compiling the above program into a program, you can execute the command in the DOS command line:

romgen > sin_ rom.mif;

1.2 Customized LPM components

Open the initial dialog box of Mega Wizard Plug_In Manager, select Create a new custom…. After clicking the Next button, select LPM_ROM under Storage, then select ACEX1K device and VHDL language mode; finally, enter the path and file name of the ROM file: F: \sing_gnt\data_rom (customized ROM component file name), click the Next button, and select the ROM control line, address line and data line. Here, select the address line width and the number of data in the ROM as 6 and 64 respectively; select the address latch control signal inclock.

For the design of address signal generator, Method 1: Design a 6-bit counter using VHDL language and generate its component symbol; Method 2: Still use LPM customization method.

1.3 Complete the top-level design

Draw the top-level schematic diagram according to Figure 3, then compile it, and the waveform simulation is shown in Figure 4.

Figure 3 Top-level circuit design of a simple sine signal generator

Figure 4 Current engineering simulation waveform output

By executing the Quartus II command Create ∠ Update/ Create Symbol Files for Current File for the current design, you can create a component symbol for the design circuit so that it can be called by the top-level design multi-function signal generator.

2. Other signal parts original program

Other signal generators can be designed by referring to the design method of the sinusoidal signal generator or directly designed using the VHDL hardware description language.

LIBRARY IEEE; -- Design of increasing sawtooth wave

USE IEEE.STD LOGIC 1164.ALL;

USE IEEE.STD LOGIC U NS IGNED.ALL;

EN TI TY signal2 IS --Increase sawtooth wave signal1

PORT (clk, reset: IN std_logic; -- reset signal reset, clock signal clk

q: OUT std_logic_vector (7 DOWNTO 0)); -- Output signal q

END signal2;

ARCHITECTURE b OF signal2 IS

BEGIN

PROCESS (clk, reset)

VARIABLE tmp: std_logic_vector(7 DOWNTO 0);

BEGIN

IF reset='0' THEN

tmp:="00000000";

E LSI T rising_ege(clk)THEN

IF tmp="11111111"THEN

tmp:="00000000";

ELSE

tmp:=tmp+1; --Incremental signal changes

END IF;

END IF;

q<=tmp:

END PROCESS ;

END b;

LIBRARY IEEE; --Square wave design

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity signal5 is --square wave signal5

PORT (clk, reset: in std_logic; -- reset signal reset, clock signal clk

q: out std_logic_vector (7 DOWNTO 0)); --Output signal q, 8-bit digital signal

END signal5;

ARCHITEECTURE A OF SIGNAL5 IS

SIGNAL; a:std_logic;

BEGIN

PROCESS (clk, reset)

YARIABLE tmp:std_logic_vector(7 downto 0);

BEQIN

IF reset='0' then

a<='0';

elsif rising_edge(clk)THEN

IF tmp="11111111" THEN

tmp:="00000000";

ELSE

tmp:=tmp+1;

END IF;

if tmp<="10000000" then

a<='1';

else

a<='0';

END IF;

END IF;

END PROCESS;

PROCESS (clk, a)

BEGIN

IF rising_edge(clk) THEN

IF a='1' THEN

q<="11111111";

ELSE

q<="00000000";

END IF;

END IF;

END PROCESS;

END a;

3 Top-level circuit design

The above six modules generate symbols for the top-level circuit to call. These modules are: decreasing sawtooth wave signal generating module signalall, increasing sawtooth wave signal generating module signal2, triangle wave signal generating module signal3, step wave signal generating module signal4, square wave signal generating module signal5 and data selector mux51. The connection of the top-level circuit is shown in Figure 5.

Figure 5 Signal generator top-level circuit

4 D/A converter connection

Select a D/A converter and connect the output of the data selector to the input of the D/A converter. There are a wide range of D/A converters available. Here we take the commonly used DAC0832 as an example. The connection circuit of DAC0832 is shown in Figure 6.

Figure 6 DAC0832 connection circuit

5 Implementation and testing

The simulation waveform of the top-level circuit of the signal generator is shown in Figure 7. Here, only the case when the input selection signal is equal to 5 is simulated. At this time, the output waveform is a square wave, and the output digital signal is periodic all 0s or all 1s.

Figure 7 Simulation waveform of the top circuit of the signal generator

The underlying circuit modules of the signal generator can also be simulated separately. For example, the step wave signal generating module signal4 is simulated. The simulation waveform is shown in FIG8 . The output digital signal changes in a step-like manner.

Figure 8 Simulation waveform of step wave signal generation module signal4

6 Conclusion

Hardware circuit design is mainly the visualization of the design ideas of related modules, a summary of the circuit diagrams of related modules and a collection of related simulation waveforms. This part is well-organized and has clear ideas, from which we can clearly see the specific modules of the design scheme and the actual diagram of the principle structure of the entire design; the program design part mainly explains the design method and design ideas of the design, and further reveals the design concept from the software design, mainly including the design of the hardware description language of the modules used in the entire design. This article has clear design ideas, and the waveform simulation is successful through QuartusII software. In particular, the LPM customization of the sine signal generator provides another way to achieve it for those who are not particularly strong in programming, deepens the understanding of the hierarchical design ideas of EDA, grasps the reform direction of teaching well, and better trains students' ability to connect theory with practice.