Design of convolutional code codec based on VHDL language

2　Convolutional encoder　　Convolutional code is usually recorded as (n ₀ ,k ₀ ,m), its coding efficiency is k ₀ /n ₀ , and m is called the constraint length. (n ₀ , k ₀ , m) convolutional code can be implemented with k ₀ inputs, n ₀ outputs, a linear finite state shift register with input storage m and a modulo 2 addition counter circuit. The encoding method of the convolutional code is 3 operation methods: discrete convolution method; generating matrix method; polynomial product method. In addition, the encoding process of convolutional codes can also be described by state diagrams, code tree diagrams and trellis diagrams. The encoder designed in this article takes into account the implementation of the hardware circuit and chooses the polynomial product method. The convolutional encoder selected for this system is shown in Figure 1. The convolutional encoder is a (2, 1, 6) auto-orthogonal convolutional encoder.
　　

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3　Large number logic decoder　　The decoding of convolutional codes can be divided into two categories: algebraic decoding and probabilistic decoding. The large number logic decoder is the most important decoding method for algebraic decoding. It can be used to correct both random errors and burst errors, but it requires the convolutional code to be a self-orthogonal code or an orthogonal code. The large-number logic decoder of the (2, 1, 6) system auto-orthogonal convolutional code selected in this article is shown in Figure 2.
　　

　　In Figure 2, the I terminal inputs the information symbol, and the P terminal inputs the verification symbol. The decoder sends each piece of information element in the received R(D) to the encoder to find the local check element, and adds it modulo 2 to the check element received later. If the two are consistent, the obtained adjoint component si is 0, otherwise it is 1. Send the added value to the associated register for storage. After receiving 7 code segments, the error correction of the 0th code segment begins . If the output of the majority logic gate is 1 at this time, it means that the information element of the 0th code segment is incorrect. At this time, the information elements of the 0th subgroup are moved to the output of the decoder, thereby correcting them. At the same time, the error correction signal is also fed back to the syndrome register to correct the syndrome to eliminate the impact of this error on the syndrome. If the large number decision gate has no output, it means that the information element of the 0th subgroup has no error, and the information element is output directly from the encoder.

4.　　VHDL design of convolutional codec

. Its program structure is characterized by dividing an engineering design (or design entity) into external (ie, port) and internal (ie, function, algorithm). After defining an external port for a design entity, other designs can directly call this entity once internal development is completed. 　　The VHDL design platform used in this design is Altera's MAX+PlusⅡ EDA software. MAX+PlusⅡ has a friendly interface and is easy to use; it supports VHDL, schematic diagrams, V language text files, and files in waveform and EDIF formats as design input; and supports any mixed design of these files; it has a gate-level simulator that can Functional simulation and timing simulation can produce accurate simulation results; support all Altera FPGA/CPLD large-scale logic devices except APEX20K, APXⅡ, Mercury, Excalibur and Stratix series. The FPGA device used in the design is Altera's FLEX series chip FLEX 10K20. The process of using MAX+PlusⅡ software for VHDL design is: 　　(1) Use Text Editor to write VHDL programs. 　　(2) Use Compiler to compile the VHDL program. 　　(3) Use Waveform Editor and Simulator to simulate and verify the VHDL program. 　　(4) Use Timing Analyzer to perform timing analysis of the chip. 　　(5) Use Floorplan Editor to arrange the chip pin positions. 　　(6) Use Programer to download the program to the chip FLEX10K20. 　　In the actual development process, the above steps need to be repeated until the established VHDL design passes all tests.
　　



　　









4.2 Convolutional encoder VHDL top level modeling (top level) and system function simulation

4.2.1 VHDL description of each functional module and top-level modeling port of
　　
　　the convolutional encoder LIBRARY IEEE;
　　
　　
　　encoder generated after compiling with MAX+PlusⅡ The graphic symbol is shown in Figure 3.

4.2.2 VHDL simulation waveform of convolutional encoder VHDL top-level modeling

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　　The convolutional encoder VHDL simulation waveform is shown in Figure 4. Before simulation, set the input information sequence datain="1111", the rate is 32 kP/s, and the corresponding clock is 31. 25μs. The simulation results show that the convolutional encoding output dataout = "1111101 0010000000001", and the corresponding rate is 64 kP/s, which is consistent with the theoretical analysis results.

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4.3 VHDL port description of the VHDL top-level modeling of the
convolution decoder 4.3.1 VHDL description of each functional module and top-level modeling port of the convolution
decoder 　　LIBRARY IEEE; the decoder graphic symbol generated after compiling with MAX+PlusⅡ is as shown in the figure 5 shown. 4.3.2 VHDL simulation waveform of convolutional decoder VHDL top-level modeling The convolutional 　　decoder VHDL simulation waveform is shown in Figure 6. Among them, the cell to be decoded datain=“11111010010000000001”, the rate is 64kP/s, and the corresponding clock is 15.625μs. The simulation results show that the decoded cell output dataout = "111 1", and the corresponding rate is 32kP/s. The actual simulation also verified the error correction situation when there are error codes in the cells to be decoded input by the convolution decoder, which is consistent with the theoretical analysis results.
　　

　　
　　
　　


　　

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5 Conclusion:　　The simulated VHDL program was downloaded to the FPGA chip FLEX10K20 and used for error control in the actual spread spectrum system, achieving satisfactory results. references
　　

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[3] Pan Song, Wang Guodong. VHDL Practical Tutorial [M]. Chengdu: University of Electronic Science and Technology Press, 2 000