Multi-protocol Data Transmission Based on TMS320F206

Digital communication equipment such as all-digital power line carriers usually require the transmission of multiple voice and data channels in a limited bandwidth data channel. The data format transmitted by such equipment is uncertain, including synchronous data format, asynchronous data format and uncertain non-isochronous data format. In addition, the rate of the data interface is also variable, and it must be able to adapt to the transmission requirements of different data rates of asynchronous data 300 b/s to 19.2 kb/s and synchronous data 300 b/s to 33.6 kb/s, so a multifunctional data interface is indispensable. When the data rate is high, ordinary microprocessors are generally unable to cope with it. Due to its special pipeline structure, DSP chips can better solve problems such as multi-channel multi-protocol high-speed data multiplexing and demultiplexing.

1 Design Concept

TMS320C2xx is a fixed-point DSP in the TMS320 series of digital signal microprocessors (Digital Signal Process, DSP) produced by American TI. The core device of this design is the digital signal processor TMS320F206, which is the only DSP chip in the C2xx series with on-chip FLASH memory.

TMS320F206 can reach a speed of 40 MIPS, and the single-cycle instruction execution time can reach 50 ns at the fastest. It has abundant on-chip and off-chip resources. The addressable memory space is 224 kB (64 kB for program space, 64 kB for data space, 64 kB for I/O space, and 32 kB for global storage space); the on-chip bidirectional access RAM is 544 B (288 B for data, 256 B for program/data); the on-chip flash memory is 32 kB; the on-chip single access RAM is 4.5 kB. There are also abundant on-chip peripherals, software programmable timers; software programmable wait state generators for program, data and I/O storage space; oscillators and phase-locked loops, which can realize clock selection: ×1, ×2, ×4 and ÷2; synchronous serial port; asynchronous serial port.

CPLD has become the first choice for digital logic circuit design in the industry due to its small size, high reliability and convenient development. This design uses Altera's MAX7000 series CPLD chip EPM7128. EPM7128 has 2,500 available gates, 128 macro cells, 8 logic gate array blocks, and a maximum user I/O number of 100, which just meets the system's requirements for digital logic circuit design.

MXL1543 is a multi-protocol software programmable data transmission interface chip. When used with the MXL1344A multi-protocol software programmable terminal resistor network, the data processing unit can quickly and easily meet the user's transmission requirements for different data formats, and flexibly select V.10, V.11, V.28, V.35 and other protocols. Therefore, this design uses MXL1543 and MXL1344A to implement a multi-protocol interface.

2 Hardware Implementation

The system consists of the following parts:

(1) The main control part with TMS320F206 as the core.

(2) The logic circuit control part with EPM7128SLC as the core.

(3) Bus driving circuit.

(4) Multi-protocol data interface circuit.

(5) Watchdog circuit.

The functions of each circuit are analyzed in detail below.

2.1 Main control circuit with DSP chip as the core

This part of the circuit consists of TMS320F206, crystal oscillator circuit and JTAG port.

The TMS320F206 port provides 7 simulation pins related to simulation circuit design, pins 76 to 82, connected to a dual-row 14-pin simulation plug. Through this JTAG port, you can use TI's XDS510 simulator to perform online simulation debugging. It must be noted that the simulation plug is a dual-row 14-pin, of which the 6th pin should be empty as a positioning pin. In the figure, EMU0/1 is a simulation pin, and a 22 kΩ pull-up resistor is added to ensure the signal rise time. PD is connected to the power supply. It is used for power supply detection to indicate whether the cable is connected and whether the target system is powered on. The other ends are connected to the corresponding ends of the DSP. Note that the distance between the simulation header and the TMS320F206 should not exceed 6 inches during wiring, otherwise a signal buffer should be added.

Another thing to note is that although TMS320F206 has 32 kB FLASH on the chip, it cannot be actually used in the debugging state. In order to make the simulation system work properly, it is necessary to add RAM for downloading programs during simulation in the designed target system. This circuit is completed with two CYC199 chips.

Pins 85 to 90 are pins of the synchronous serial port. In this design, this synchronous serial port is mainly used to process synchronous data. The synchronous serial port requires three signals:

The clock signal (CLKX/CLKR) is generated and input by the CPLD; the frame synchronization signal (FSX/FSR) is generated and input by the CPLD; the data signal, the sending pin (DX) is connected to the TTL sending end of the multi-protocol interface chip, and the receiving pin (DR) is connected to the TTL receiving end of the multi-protocol interface chip.

The asynchronous serial port (ASP) on the chip can provide convenient serial data communication. There are 4 registers in the chip: asynchronous data transmission and reception register (ADTR), asynchronous serial port control register (ASPCR), I/O status register (IOSR), and baud rate division register. There are also 2 registers that are not accessible to programmers: asynchronous serial port transmission shift register (AXSR) and asynchronous serial port reception shift register (ARSR). There are 6 pins TX, RX, IO0, IO1, IO2, and IO3. In this design, TX and RX are used to transmit asynchronous data with the host computer, and IO0~IO3 are used as general I/O ports.

This design uses the general-purpose input pin BIO, the general-purpose output pin XF and external interrupts to handle the user's asynchronous data transmission.

Pins D0~D15 and A8~A12 of TMS320F206 are connected to CPLD to expand the I/O port and realize other logic functions.

2.2 Logic Control Circuit

The required logic control is realized by the CPLD chip EPM7128 of Altera Company, and the I/O port expansion of TMS320F206 is realized. Among them, the following need to be controlled:

(1) Chip select line CS and direction DIR of HPI drive circuit 74F245;

(2) Perform software programming on the interface chip MXL1344A, MXL1543 and select the data transmission protocol mode;

(3) Control of the X25043 watchdog circuit;

(4) Output HPI-8 port control signal and perform effective data exchange with HPI-8 port;

(5) 4-16 decoder circuit, frequency divider circuit, D flip-flop circuit, latch circuit, selection switch circuit, etc. required by the system.

It is composed of EPM7128SLC EPLD chip and JTAG port, which can realize online programming. The reset circuit is composed of X25043 and power-on reset circuit 2R3, 2C1.

2.3 Bus driver circuit

The bus driver uses two 74HC245 chips to form the HPI-8 interface circuit. In order to overcome interference, each bus should be connected in series with a 100 Ω resistor.

2.4 Multi-protocol data interface circuit

The above interface circuit consists of three parts:

(1) MAX485 interface circuit: This circuit completes the interface level conversion between TMS320F206 and the network management system through the serial port.

(2) MAX232 interface circuit: This part of the circuit mainly completes the level conversion between the flow control signal (CTS/RTS, DTR/DSR) and the TTL circuit during asynchronous data transmission.

(3) MXL1543, MXL1344A: This part of the circuit mainly completes the selection of multiple protocols. Through software programming of M0, M1, and M2, the conversion of multiple protocols can be realized. Among them, there are more than a dozen protocols such as RS 530, X.21, and V.35.

3 Software Implementation

The software consists of the following 6 parts, each with the following functions:

(1) Main program part;

(2) F206 initialization part: realize the initialization of each register of F206;

(3) Synchronous serial port part: realizes the processing of synchronous data;

(4) Asynchronous serial port part: realize data communication with the host computer;

(5) X25043 software: password setting and implementation of watchdog circuit processing;

(6) With HPI-8 data processing part: realize data exchange with HPI-8 host interface.

The main program mainly completes the configuration of the default data format, register initialization, querying the data configuration of the host computer, and interacting with the external circuit through HPI. The processing of asynchronous data and synchronous data is completed in the asynchronous interrupt and synchronous interrupt subroutines.

4 Conclusion

The above design uses TMS320F206 DSP chip to realize core control, EPM7128 to realize peripheral logic control, and MXL1543 and MXL1344A special chips to realize protocol conversion, which solves the problem of high-speed multi-channel multi-protocol data transmission. After logic analyzer testing and bit error testing, all indicators meet user requirements.