Arbitrary signal generator based on DSP and AD9852

Direct digital frequency synthesis (DDS) technology is the third generation frequency synthesis technology that has developed rapidly with the development of digital integrated circuits and microelectronics technology, following direct frequency synthesis and indirect frequency synthesis. DDS technology has the advantages of relatively wide bandwidth, short frequency conversion time, and high frequency resolution. The output phase is continuous, and the frequency, phase, and amplitude can be programmed. It is often used for high-precision frequency synthesis and arbitrary signal generation. In the design of the engine electronic control unit (ECU) hardware-in-the-loop simulation system, this article uses TMS320 LF2407A to control two AD9852s to generate two synchronous arbitrary signals to simulate the real signals when the engine is working.

1 Introduction to AD9852 and TMS320LF2407A

AD9852 is a new direct digital frequency synthesizer produced by Analog Devices in the United States. It has the characteristics of fast frequency conversion speed, high spectrum purity, wide operating temperature range, and high integration. The operating voltage is 3.3 V. There is a 4 to 20 times programmable clock multiplication circuit on the chip. The maximum system clock can reach 300 MHz, the output frequency can reach 120 MHz, and the frequency conversion speed is less than 1 μs. There are 12-bit D/A converter, 48-bit programmable frequency register and 14-bit programmable phase register inside. It has a 12-bit amplitude tuning function and can generate highly stable analog signals with programmable frequency, phase and amplitude.

TMS320LF2407A is a fixed-point DSP controller launched by TI. It uses high-performance static CMOS technology to reduce the power supply voltage to 3.3 V, reducing the power consumption of the controller; the shortest instruction is 25 ns, and has strong real-time control Capability; the chip has 32 kB of encryptable FLASH program memory, 2.5 kB of RAM, and an A/D converter with a 500 ns conversion time. The on-chip event manager provides a PWM interface and I/O that can meet various motor control requirements. function, in addition, SPI, SCI and CAN controllers are integrated on-chip.

2 Hardware interface circuit between TMS320LF2407A and AD9852

In this system, the function of TMS320LF2407A is to calculate the waveform parameters of the signal to be generated, and send the control word to the internal control register of AD9852 to achieve programmable arbitrary signal generation. There are two ways of data transmission: serial and parallel. The maximum serial transmission rate is 10 MHz and the maximum parallel transmission rate is 100 MHz. In order to save DSP resources, on the premise of meeting the system requirements, a serial port connection method is adopted, and the serial peripheral interface (SPI) on the TMSLF2407A chip is used to control the AD9852. The schematic block diagram of the interface circuit is shown in Figure 1.

3 Serial communication working process of AD9852

The serial interface of AD9852 is compatible with the SPI interface of TMS320LF2407A, and serial data transmission control can be realized through 5 ports. PRD/CSB is a multiplexed signal. In the serial working state, CSB serves as the chip select signal of the AD9852 serial bus. I/O RESET is the serial port bus reset signal. SCLK is the serial port clock signal. The system uses a 2-wire serial port communication mode. , use the SDIO port for bidirectional input and output operations, and the I/O UD is the update clock signal. The timing sequence of serial communication work is shown in Figure 2.

The serial communication cycle of AD9852 is divided into 2 stages. The first 8 rising edges of SCLK correspond to the instruction cycle. In the instruction cycle, the user sends command words to the serial port controller of AD9852 to control the subsequent serial data transmission. The data transmission cycle starts from the 9th rising edge of SCLK. Input data is written on the rising edge of the clock, and output data is read out on the falling edge of the clock. The data transmitted by the serial port is first written into the I/O cache register. When the system receives a valid update signal, the data is written into the internal control register group to complete the corresponding function. When the communication cycle is completed, the AD9852 serial port controller believes that the rising edges of the next eight system clocks correspond to the instruction words of the next communication cycle.

When a high level input appears on the I/O SESET pin, the current communication cycle will be terminated immediately. When the I/O RESET pin status returns to low level, the AD9852 serial port controller considers the next 8 system clocks The rising edge of corresponds to the instruction word of the next communication cycle, which is very beneficial to maintaining communication synchronization.

4 2 pieces of AD9852 working simultaneously

The key to achieving phase synchronization of the output signal waveforms of two AD9852s is to make them work under the same system clock. The maximum phase error between the system clocks of each AD9852 cannot exceed 1 cycle. The system clock of the AD9852 can be directly provided by the reference clock, or the reference clock can be amplified through an internal clock multiplier. The asynchronous update clock is synchronized with the system clock after passing through the edge detection circuit inside the AD9852, forming a rising edge, which triggers the update content of the internal control register. Therefore, to achieve synchronization of two AD9852s, their reference clock must be synchronized with the rising edge of the update signal. The following are some points that need to be paid attention to to ensure that the two AD9852s work synchronously.

4.1 Reference clock signal

The AD9852 reference clock has two forms: differential input and single-ended input. Since the differential clock has shorter rise and fall times and the smallest jitter rate at the pulse edge, it can effectively reduce the phase error between the two AD9852 reference clocks. Therefore, This system adopts the reference signal differential input method. For the differential input mode, the input signal can be a square wave or a sine wave. It is recommended to use the MAX9371 of MAXIM Company, which can convert the ordinary clock signal into the differential clock signal required by the system. In order to achieve reference clock synchronization, two AD9852s share a crystal oscillator. The signals output by the crystal oscillator are first sent to two differential clock generators respectively, and then input into two AD9852s after conversion. In order to ensure that the delay time of each AD9852 reference clock signal during transmission is consistent, the clock signal routing distance must be the same during PCB wiring.

4.2 Update clock signal

When programming the AD9852, the serial input data is cached in the internal I/O buffer register, which will not affect the working status of the AD9852; after the rising edge of the update clock signal arrives, the I/O buffer register is triggered. The data is transferred to the internal control register, and only then can the corresponding functions be completed and the control of the output signal realized. There are two ways to generate the update clock signal. One is automatically generated internally by the AD9852 chip. The user can program the frequency of the update clock to generate a fixed-period internal update clock. The other is the user provides an external update clock. This When the AD9852I/OUD pin is an input pin, the signal is provided by the external controller. To achieve synchronization between two AD9852s, it is necessary to ensure that the rising edges of their update clock signals come at the same time, so the system adopts an external clock update method. Using an I/O port of the DSP to connect to the I/O UD of the AD9852, precise control of the rising edge of the update clock signal can be achieved through software. The wiring requirements for the external update clock signal are the same as for the reference clock.

4.3 Reference clock multiplier

The working clock of AD9852 is as high as 300 MHz. In order to reduce the interference of the clock signal, the system should use a low-frequency clock signal source, and then use the reference clock multiplier on the AD9852 chip to achieve 4 to 20 times the external reference clock. The phase-locked loop circuit of the reference clock multiplier has two working states: locking state and obtaining locking state. In the locked state, the system clock signal and the reference clock signal can remain synchronized. However, when a control command is sent to the AD9852, within a short period of time after its reference clock multiplier operates, the phase-locked loop cannot lock immediately and still operates in a locked state. At this time, the number of system clock cycles transmitted to the AD9852 phase accumulator is uncontrollable, which may cause the phases of the output signals of the two AD9852s to be out of sync. Therefore, after the system is initialized, you must first ensure that the phase-locked loop is locked. status, and then the various control words inside AD9852 can be updated. The typical locking time of the AD9852 on-chip phase-locked loop is about 400μs. It is recommended to leave at least 1 ms for the phase-locked loop to enter the locked state.

5 AD9852 control flow

(1) Power on the system, and the DSP sends a reset signal to the AD9852. This signal needs to remain high for at least 10 reference clock cycles.

(2) Set S/P SELECT to 0 to select the serial data input method.

(3) Send control words to each AD9852 in turn to change the working state of each AD9852 from the default internal update clock mode to the external clock update mode.

(4) Write the control word for the AD9852 clock multiplier operation into the I/O buffer register of each AD9852 in sequence, and then the DSP sends an external update clock to update the internal control register of each AD9852.

(5) The DSP sends an external update signal and waits at least 1.0 ms for the AD9852 internal phase-locked loop to lock. Then the DSP sends the relevant signal waveform parameters to the AD9852, and updates the contents of their internal control registers synchronously, so that the two AD9852s output synchronous analog signals.

6 Conclusion

Using DSP to control the knock signal and camshaft signal generated by AD9852 can meet the requirements of the engine electronic control unit hardware-in-the-loop simulation system in terms of accuracy and real-time performance. On the basis of this system, it can be further expanded to be used simultaneously with multiple DDS chips, making it suitable for more hardware-in-the-loop simulation systems.