Energy Optimization for Modern FPGA Designs

Reducing FPGA power consumption can bring many benefits, such as improving reliability, reducing cooling costs, simplifying power supplies and power delivery, and extending battery life in portable systems. Low-power design without compromising performance requires both a power-efficient FPGA architecture and good design practices that can harness the architectural components.

This article will introduce FPGA power consumption, popular low-power features, and user choices that affect power consumption. It will also explore recent low-power research to gain insight into future trends in power-efficient FPGAs.

1 Components of power consumption

The power consumption of an FPGA consists of two components: dynamic power and static power. Dynamic power is generated when signals charge capacitive nodes. These capacitive nodes can be internal logic blocks, wiring wires in the interconnect fabric , external package pins, or board traces driven by chip outputs. The total dynamic power consumption of an FPGA is the combined power consumption from charging all capacitive nodes.

Static power consumption is independent of circuit activity and can be generated by transistor leakage current or bias current. The total static power consumption is the sum of the leakage power of each transistor and all bias currents in the FPGA. Dynamic power consumption depends on the active capacitance side and can improve as the size of the transistors decreases. However, this increases static power consumption because smaller transistors have higher leakage currents. Therefore, static power consumption accounts for an increasing proportion of the total power consumption of the integrated circuit .

As shown in Figure 1, power consumption is highly dependent on supply voltage and temperature. Reducing the FPGA supply voltage decreases dynamic power consumption quadratically and leakage power consumption exponentially. Increasing temperature causes leakage power consumption to increase exponentially. For example, increasing the temperature from 85°C to 100°C increases leakage power consumption by 25%.

Figure 1 Effects of voltage and temperature on power consumption

2 Power consumption breakdown

Let's analyze the decomposition of the total FPGA power consumption to understand where the power consumption mainly lies. FPGA power consumption is design-dependent, that is, it depends on the device family, clock frequency, toggle rate, and resource utilization.

Taking Xilinx Spartan-3 XC3S1000 FPGA as an example, it is assumed that the clock frequency is 100MHz , the toggle rate is 12.5%, and the resource utilization is taken from the typical values ​​of various actual design benchmark tests.

Figure 2 shows the XC3S1000’s active and standby power breakdown. According to the report, active power is the power consumed when the design is active at high temperatures, and includes both dynamic and static power. Standby power is the power consumed when the design is idle, and consists of static power at rated temperature. It is not surprising that the CLB accounts for the largest portion of active and standby power, but other blocks also generate significant power. I/O and clock circuits account for 1/3 of the total active power, and even more if high-power I/O standards are used.

Figure 2 Typical power consumption breakdown of a Spartan-3 XC3S1000 FPGA

Configuration circuits and clock circuits account for nearly 1/2 of the standby power consumption, which is largely due to bias current. Therefore, to reduce the total power consumption of the chip, multiple solutions must be adopted for all major power consumption devices.

3 Low power design

A variety of power-driven design techniques are used in FPGA design. Taking the Xilinx Virtex series as an example, because the configuration storage unit can account for 1/3 of the number of transistors in the FPGA, a low leakage current "midox" transistor is used in this series to reduce the leakage current of the storage unit. In order to reduce static power consumption, transistors with longer channels and higher thresholds are also fully adopted. Dynamic power consumption issues are solved with low-capacitance circuits and custom modules. The power consumption of the multiplier in the DSP module is less than 20% of the multiplier built by the FPGA architecture. Given that manufacturing deviations can cause a wide range of leakage current distribution, low leakage current devices can be screened out to effectively provide devices with core leakage power consumption below 60%.

In addition to incorporating FPGA design, there are many design choices that affect FPGA power consumption. Some of these choices are analyzed below.

3.1 Power consumption estimation

Power estimation is a critical step in low-power design. Although the most accurate way to determine FPGA power consumption is through hardware measurement, power estimation helps identify high-power blocks and can be used to develop a power budget early in the design phase.

As shown in Figure 1, certain external factors have an exponential impact on power consumption; small changes in the environment can cause significant changes in the estimated power consumption. Although it is difficult to achieve accuracy using power estimation tools, they can still provide excellent guidance for power optimization by identifying high power consumption blocks.

3.2 Voltage and Temperature Control

As shown in Figure 1, both voltage and temperature reduction can significantly reduce leakage current. Reducing the supply voltage by 5% can reduce power consumption by 10%. The supply voltage can be easily adjusted by changing the power supply configuration. Current FPGAs do not support a wide range of voltage adjustment, and the recommended voltage range is usually ±5%. Junction temperature can be reduced using cooling solutions such as heat sinks and airflow. Reducing the temperature by 20°C can reduce leakage power consumption by more than 25%. Reducing the temperature can also exponentially improve the reliability of the chip. Studies have shown that reducing the temperature by 20°C can extend the overall life of the chip by 10 times.

3.3 Suspend and Sleep Mode

Modes such as suspend and sleep can effectively reduce power consumption. Taking the Xilinx Spartan-3A FPGA as an example, the device provides two low-power idle states. In suspend mode, the circuit on the VCCAUX power supply is disabled to reduce leakage power consumption and eliminate bias current, which can reduce static power consumption by more than 40%. The chip configuration and circuit status are still maintained during suspension. The wake-up pin can be set to exit the suspend mode. This process takes less than 1ms.

Hibernate mode allows all power regulators to be turned off , resulting in zero power consumption. To restart, the power supply must be turned back on and the device configured, which takes tens of milliseconds. After power is removed, all I/Os are in a high impedance state. If any I/O needs to be actively active in hibernate mode, the corresponding I/O bank must remain powered, which consumes a small amount of standby power.

3.4 I/O Standard Solution

The power consumption levels of different I/O standards vary widely. Choosing a low-power I/O standard can significantly reduce power consumption at the expense of speed or logic utilization. For example, LVDS is a power hog, drawing 3mA per input pair and 9mA per output pair. Therefore, from a power perspective, LVDS should be used only when the system specification requires it or when the highest performance is needed.

A lower power and higher performance alternative to LVDS is HSTL or SSTL, but both still consume 3mA per input. If possible, it is recommended to switch to LVCMOS inputs. In addition, the DCI standard is a power hog. When interfacing to memory devices such as RLDRAM, consider using ODT on the memory and LVDCI on the FPGA to reduce power consumption.

3.5 Embedded Modules

Embedded modules are custom designed so that their size and switch capacitance are smaller than those of programmable logic. These modules consume 1/5 to 1/12 of the power of equivalent programmable logic.

Replacing programmable architecture with embedded modules can significantly reduce power consumption. If the design shrinks and can fit into a smaller device, using embedded modules can reduce static power consumption. One potential disadvantage is that very simple functions may not be implemented more efficiently using large embedded modules.

3.6 Clock Generator

Considering power consumption in clock generation can reduce power consumption. Digital clock managers are widely used to generate clocks of different frequencies or phases. However, the power consumed by DCMs is a significant portion of VCCAUX; therefore, the use of DCMs should be limited as much as possible. By using multiple outputs such as CLK2X, CLKDV, and CLKFX, a single DCM can often generate multiple clocks. This is a lower power solution than using multiple DCMs for the same function.

3.7 Block RAM Construction

Multiple block RAMs can often be combined to form a large RAM. The way they are combined can have significant implications for power consumption. The timing-driven approach is to access all RAMs in parallel. For example, four 2k×9 RAMs can be used to form a 2k×36 RAM. This larger RAM has the same access time as a single block RAM; however, each access consumes the same power as the four block RAMs combined.

A low-power solution is to use four 512×36b RAMs to form the same 2k×36b RAM. Each access is pre-decoded to select one of the four block RAMs. Although pre-decoding increases the access time, the power consumption of each access to the larger RAM is roughly the same as that of a single block RAM.

4 Low Power Consumption Research

4.1 Lowering the voltage

Reducing voltage is one of the most effective ways to reduce power consumption, and the resulting performance degradation is acceptable for many designs that do not require the highest performance. However, the current operating voltage range of FPGAs is very small and cannot be used on some voltage-sensitive circuits.

In Xilinx research labs, CLB circuits were redesigned to operate at much lower voltages to provide a generous performance tradeoff at lower power consumption. For example, for 90nm processes, a 200mV drop in voltage reduces power consumption by 40% with a 25% performance loss at best, and a 400mV drop in voltage reduces power consumption by 70% with a 55% performance loss at best.

4.2 Fine-grained Power Switch

One of the unique overheads of programmable logic design is that not all on-chip resources are used for a given design. However, unused resources remain powered and contribute to the total power consumption in the form of leakage power. Block-level power switches can individually turn off power to unused blocks. Each block is coupled to the power supply through a power switch. When the switch is closed, the block is operational. When the switch is open, the block is effectively disconnected from the power supply, reducing leakage power consumption by 1/50 to 1/100. The granularity of the power switch can be as small as a single CLB and block RAM. In the design, these power switches can be programmed through the configuration bitstream, or they can be controlled directly by the user or through access ports. Benchmark test results of actual designs show that fine-grained power switches can reduce leakage power consumption by 30%.

4.3 Deep Sleep Mode

One of the main requirements for portable electronic products is that the device consumes very little or no power when idle. Taking the Xilinx Spartan-3A FPGA as an example, the chip can achieve this by entering a sleep mode, which requires external control, wakes up slowly, and cannot restore the FPGA state. The design dynamically controls the above fine-grained power switch to shut down all internal modules and only keep the configuration and circuit state storage components powered. The resulting state is a deep sleep mode with leakage power consumption of 1% to 2% of the rated power consumption, saves the FPGA state, and exits this mode in just a few microseconds.

4.4 Heterogeneous Architecture

The maximum clock frequency of a circuit is determined by the delays of its timing-critical paths. Non-critical paths can be slower without affecting overall chip performance. In a large system, there can be a few speed-critical blocks (such as datapaths in a processor) and other blocks can be non-critical (such as caches).

Today’s FPGAs are identical in terms of power and speed; each CLB has the same power and speed characteristics. Heterogeneous architectures can reduce power by including some low-power (and slower) blocks by implementing non-critical blocks within the low-power blocks. This does not affect overall chip performance because timing-critical blocks do not lose performance.

One way to create a heterogeneous architecture is to allocate two core power rails, a high voltage rail (VDDH) and a low voltage rail (VDDL). Each device of the FPGA selects one of the two with an embedded power switch and uses high speed or low power characteristics accordingly. After the detailed timing of the design is determined, the voltage selection is completed, so only non-critical blocks should be powered by VDDL.

Another way to create a heterogeneous architecture is to divide the FPGA into different regions and pre-engineer each of these regions to have high speed and low power characteristics. These regions can be implemented with different supply voltages, different thresholds, or through a number of other design trade-offs. To avoid performance degradation, the design tools must map the timing-critical devices of the design into the high-speed region and the non-critical devices into the low-power region.

4.5 Low-Swing Signaling

As FPGAs grow in size, the on-chip programmable interconnect consumes more power. An effective way to reduce this communication power is to use low-swing signaling, where the voltage swing on the wire is much lower than the supply voltage swing. Today, low-swing signaling is common when communicating over highly capacitive wires such as buses or off-chip links. Low-swing drivers and receivers are more complex than CMOS buffers and therefore take up more chip area. However, as on-chip interconnects become a larger component of overall power consumption, the power benefits of low-swing signaling will justify the added design complexity. Of course, the FPGA user will not see the difference in internal signal voltages.

Figure 3 shows an FPGA architecture with some of the above concepts. Its programmable heterogeneous architecture consists of two zones: high speed and low power. An on-chip power mode controller manages various power reduction modes, namely deep sleep mode, suspend mode, and hibernation mode. Within the architecture, dedicated power switches can be used to turn off the power to each logic block. Communication signals through the wiring rack flow through low-swing drivers and receivers to reduce interconnect power consumption.

Figure 3 Conceptual architecture with multiple power reduction solutions

5 Conclusion

In addition to the energy optimization schemes currently used in modern FPGA designs, some user design decisions can also produce significant power consumption benefits. It is foreseeable that in the future new technologies there will be more aggressive architectural solutions to curb power consumption, thus making new FPGA applications possible.