Design of DSP high-speed host computer interface based on USB protocol

Abstract: The DSP system of missile-borne signal processor requires a high-speed and simple host computer interface to realize the real-time monitoring of large data volume variables and online program loading functions. The USB interface is the preferred choice due to its simplicity, high speed and universality. This paper introduces a design method of ADSP-TS101 extended USB interface based on USB interface chip (CY7C68013A) and FPGA. This method uses the Link-port interface of DSP to perform high-speed data exchange in DMA mode. At present, this design has been maturely and reliably applied to a missile-borne signal processing system.
Keywords: USB; DSP Linkport; PC interface; high-speed data exchange

0 Introduction
The DSP device (ADSP-TS101) of ADI Company has the advantages of strong floating-point real-time processing capability and good parallelism, so it is widely used in missile-borne signal processing systems. As the missile-borne main processor, it is necessary to use the host computer to monitor and record the large data volume software variables in real time during the system test of the missile. This requires a high-speed communication interface for uplink transmission to the host computer, and the data rate of the uplink data needs to be greater than 6 MB/s. At the same time, this communication interface must also have bidirectional characteristics, and online program loading and burning can be realized through data downlink. Such a communication interface must also have the characteristics of simple device connection, strong versatility, and remote (greater than 3m) data transmission.
Although the external bus interface and link port (Linkport interface) of ADSP-TS101 are very fast, the connection is complex and difficult to transmit over long lines, and they do not have the above-mentioned required characteristics. The above-mentioned application requirements can be realized by adding an adapter circuit implemented by FPGA to the Linkport bus interface of DSP and expanding the USB 2.0 interface. The specific implementation plan will be introduced below.

1 System overall plan
The overall plan of system implementation is shown in Figure 1.

In this solution, the USB interface chip is Cypress's CY7C68013A. This chip is one of Cypress's FX2 series USB 2.0 integrated microcontrollers. It integrates USB 2.0 transceiver, SIE, enhanced 8051 microcontroller and GPIF, and is an excellent high-speed USB peripheral controller. The built-in 8051 microcontroller is independent of the USB data channel, and most of the USB 1.1 and USB 2.0 protocols are implemented by SIE; USB FIFO and external slave FIFO are mapped to the same 8 512 B RAM modules to achieve seamless connection between internal and external transmission, and can obtain higher bandwidth at a lower cost; 8.5 KB internal RAM space can run more complex firmware and realize software configuration of hardware. GPIF is a flexible 8/16-bit parallel port driven by a user-programmable finite state machine. The programmable GPIF vector forms a GPIF waveform to match the timing of the controlled interface.
ADSP-TS101 is the main DSP chip on board, with 4 link ports. Each link port can perform bidirectional data transmission with 8 bits on both edges of the clock, with a rate of up to 250 MB/s. Through this interface, the DSP sends the pre-observed variable results to the host computer in DMA mode in each processing frame.
FPGA implements bidirectional data buffering and interface protocol conversion between the Linkport interface of ADSP-TS101 and CY7C68013A. Considering that the FIFO capacity in CY7C68013A is smaller than the amount of data pre-sent or received in a processing frame of DSP, a large-capacity FIFO for both upstream and downstream is set in FPGA for data buffering to reduce the interference with the parallel pipeline running programs in DSP. Here, since the instantaneous data rate of the DSP link port is much higher than the transmission rate of the USB chip (theoretical upper limit is 60 MB/s), the data transmission of the DSP port of the FIFO is: one processing frame is only operated once, while the USB chip end is divided into multiple operations.
Due to space limitations, the following will focus on the design of the upstream channel with high transmission data rate requirements and high design difficulty.

2 FPGA Simulation Linkport Design
FPGA needs to simulate the interface timing of the Linkport. The hardware connection diagram between FPGA and DSP is shown in Figure 2.

The Link protocol completes bidirectional data transmission through an 8-bit parallel data bus, and the data bus is also coordinated with the corresponding clock signal lines LxCLKIN and LxCLKOUT.
2.1 Transmission protocol of the Linkport
When the Linkport transmits data, a 4-word group (16 B) is transmitted every 8 cycles, and a byte is transmitted at both the rising and falling edges of the clock. During the transmission process, the transmitter will detect the LxCLKOUT signal of the receiver. Only when the receiver sets its LxCLKOUT to high, that is, the receiver is in receiving mode and has an idle buffer, can the transmitter start the next transmission process. The
transmission start process is shown in Figure 3. The transmitter drives the signal LxCLKOUT to a low level to send a token request to the receiver. After sending the token request, the transmitter waits for 6 cycles and verifies whether LxCLKIN is still high. If so, the transmission process is started. After the transmission process starts for one cycle, the receiver drives the LxCLKIN of the transmitter to a low level as a connection test. If the receiver cannot receive another 4-word group after receiving the current 4-word group, the receiver keeps LxCLKIN low. In this case, the LxCLKIN signal is disabled after the buffer is free. If the buffer is empty, the receiver will set LxCLKIN high.

As a synchronization signal, the LxCLKOUT signal is driven by the transmitter. Data is latched into the receiving buffer at the rising and falling edges of LxCLKOUT. Both the transmitting and receiving buffers are 128b wide. The LxCLKIN signal is driven by the receiving end and sent to the transmitting end. It is usually used as a "wait" indicator signal, but the LxCLKIN signal can also be used as a connection test signal to ensure that the receiving end can correctly receive the current transmission data.
When the LxCLKIN signal is used as a wait indicator signal, the receiving end drives the LxCLKIN signal to a low level. If the LxCLKIN signal remains in a low state, the transmitting end can complete the current 4-word group transmission, but cannot start the next vertical word group transmission. If there is still remaining data to be transmitted, the transmitting end needs to set LxCLKOUT low and wait for the receiving end to drive LxCLKIN to a high level. If LxCLKIN becomes high before the arrival of the 12th clock edge, the next transmission will be a new 4-word group.
2.2 Linkport logic design in FPGA
Since the Link protocol uses dual clock edges to transmit data, and in synchronous FPGA systems, only the rising edge of a single clock is generally used to complete operations, it is necessary to set the FPGA system operating frequency SCLK to twice the Link clock. Then the two-frequency output of the clock is used as the LxCLKOUT signal, and the valid data is updated on the rising edge of SCLK.
The Linkport interface module circuit in the FPGA is fully compatible with the Linkport of ADSP-TS101, and uses bidirectional double data transmission DDR technology to achieve bidirectional double data transmission. The Linkport interface module circuit in the FPGA is shown in Figure 4.

FIG. 5 is a timing simulation diagram of the Linkport receiving port for realizing DSP data uplink in FPGA (based on Modelsim simulation software).

One of the major features of the Link port protocol is that it is possible to choose whether to use the check bit VERE when sending and receiving data. The enablement or disablement of VERE can be set through the register in ADSP-TS101, or by setting the Verein signal in the FPGA module high or low. This design sets the enablement or disablement of the VERE signal in the FPGA. When VERE is enabled, the output signal Rx_Vere_Bad in the FPGA module is used to indicate whether the last received 128 b data is correct. Since there are two benefits of using VERE, one is to ensure the integrity of the data; the other is to reduce the possibility of data overlap when transmitting data in a system where the two clocks are not strictly consistent. Therefore, a transmission mode with data check is adopted in the design.

3 USB transmission design
3.1 Determination of transmission mode
The CY7C68013A chip has two interface working modes: GPIF mode and slave FIFO mode. In this design, the USB data transmission storage module is responsible for completing the high-speed transmission of a large amount of data generated by the storage algorithm. Since it does not involve the control of the external circuit, the GPIF mode is not selected, but the Slave FIFO mode is selected for connection. During data transmission, the Slave FIFO interface mode, batch transmission, automatic input (AUTOIN) mode are used, and the EP6 port is used as the upstream input buffer. The Slave FIFO interface mode of CY7C68013A is shown in Figure 6.

3.2 EZ-USB FX2 timing design
In the FPGA of this design, the functional logic of the external host controller is designed as shown in Figure 6. Since the data transmission rate of the Linkport port on the DSP side is very high, and the rate on the USB side may not match the data rate of the Linkport port, a 2KB FIFO is opened in the FPGA. The data uploaded via the Linkport is first transferred to the FIFO, and then uploaded to the host via the USB port. In order to ensure the integrity of data transmission, the data transmission rate of the USB is designed to be 1/8 of the DSP Link port. Here, the FPGA logic is simulated using the Modelsim software, and the simulation results are shown in Figure 7.

In Figure 7, the data in DSP_Data is written into the FPGA's FIFO at the rising and falling edges of the LxCLKIN clock, and then the data in the FIFO is output from the data line USB_Data to the FD data line of EZ-USB FX2, and finally transmitted to the host via USB. The data rate of USB_Data in the figure is obviously only 1/8 of the data rate of DSP_Data, which meets the design requirements.

When uploading, the asynchronous automatic input method is adopted. The asynchronous write timing of the EZ-USB FX2 chip FIFO is shown in Figure 8. According to this timing, in this design, the USB_Data signal output by the FPGA is provided to the FD data line of the USB, and the USB_SLWR output by the FPGA is provided to the SLWR of the USB. The USB end can write the data in the data line FD into the FX2 chip FIFO at the falling edge of the SLWR, and transmit it to the host by the USB.

4 Conclusion
This paper focuses on the hardware design of the data uplink channel of the DSP extended USB interface. This system has been tested and verified. Through this extended USB interface, with the customized upper computer software, the average rate of DSP data upload to the PC reaches more than 8 MB/s. The connection is reliable and stable, meeting the data rate requirements for real-time monitoring of DSP variables. At the same time, the program loading and burning functions can be completed through this interface. Only a PC with a USB interface is needed to complete the real-time test and online program loading of the missile-borne DSP system. It is simple, universal, convenient, and has significant engineering practical value.