New voice compression chip CT8022

　　CT8022 is a dedicated DSP chip developed by DSPG that can implement multiple compression algorithms. It can accept 64/128kbits/s 8bit A/μ data or 16bit linear data provided by the external serial A/D, and realize full/half-duplex compression and decompression to compress it into a value determined by the host through the command word. Format. Can be compressed to 8.5/6.3/5.3/4.8/4.1kbits/s data. When the compression is 6.3/5.3kbits/s, it complies with ITU-G. 723.1 standard. CT8022 has built-in real-time echo cancellation and automatic gain control circuits. When the sampling clocks of the sending end and the receiving end are not synchronized, the system can automatically add or delete frames. In addition, CT8022 also provides the generation and detection functions of DTMF signal and call continue tone. Can be applied to H. 323 and H. 324 multimedia video phone/video conferencing and other systems can also be used to implement digital data/voice simultaneous interpretation (DSVD) technology.

1 Pin description
→标题EN(开始)　　C 标题EN(结束)←T8022 has 128 pins, divided into 6 categories. 　　(1) Host interface pins 　　HSTDB0~7: host data bus. 　　HSTAB0～3: Host address line. Among them, HSTAB0 is used to select the high 8 bits or low 8 bits of the 16-bit control word. When it is 0, it selects the low 8 bits, and when it is 1, it selects the high 8 bits. 　　HSTRDN: Host read permission signal. Allows the host to read data from the host interface register selected after decoding by HSTAB1~3. 　　HSTWRN: Host write enable signal. Allows the host to write data to the host interface register selected after decoding by HSTAB1~3. 　　HSTCSN: Host interface selection signal. When reading and writing to CT8022, this pin works together with HSTRDN, HSTWRN and HSTAB0~3. When HSTCSN is valid, HSTAB0~3 should remain unchanged. In DMA mode, this signal should be set to invalid. 　　(2) Data/program memory pins 　　MDB0~15: external data memory data bus. 　　ADDR0～15: External data memory address bus. 　　BSEL: External data bus byte select. This pin is useful when connecting to external memory that is not 16-bit wide. 　　DRDN: External data storage read allowed. 　　DWRN: External data memory write enabled. 　　PRDN: External program memory read allowed. 　　PRWN: External program memory write allowed. 　　CREADN: Read external program and data memory pins simultaneously. 　　DCSN: External data memory chip select signal. Do not connect to ground when not in use. 　　(3) Clock pin 　　SLK: CODEC interface shift clock. 　　FSYNC: CODEC interface frame synchronization clock. 　　XIN: Crystal/external clock input. XOUT: Crystal output terminal. 　　CLKOUT: The core frequency of CT8022 voice compression chip. It is obtained by dividing the internal frequency 45.056MHz. The frequency division factor can be set through commands. 　　PLLR, PLLC, PLLT, AVCC, AGND: PLL support pins. The connection method is shown in Figure 1. 　　PLLBYPASS: Disables the internal PLL. Used when the XIN terminal is directly connected to an external 90.112MHz clock. ^?　　(4) CODEC pin 　　DX0: used to serially output the decompressed signal to CODEC0. 　　DR0: used to serially input 8/16bit format signals from CODEC0. 　　DX1: used to serially output the decompressed signal to CODEC1. 　　DR1: used to serially input 8/16bit format signals from CODEC1. 　　(5) DMA pin 　　TXDREQ: DMA send request signal. Data transmission can use DMA mode or host access mode. The specific method can be controlled by writing control commands to the hardware control register (HCR) during initialization. 　　TXDACKN: DMA transmission allowed. RXDREQ: DMA receive request signal. RXDACKN: DMA reception permission signal.
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　　(6) Other pins
　　GND1~18: ground pins. 　　VCC1～18: Connect to 5V power supply. IRQN: Interrupt request signal. RSTN: reset port. 　　GPIO0～7: General I/O pins. Compatible with the previous series of this device, CT8015. 　　BRQN, ABORTN, EINTN: reserved pins. Can be connected to VCC through a 10kΩ pull-up resistor. BGRNTN, BRDN: reserved, not connected. 　　EXTP, BMODE, DBG, BOOT, URST, TEST: reserved, grounded. 　　It should be noted that: in the above pin names, if the last letter is N, it means that the pin is active low.





　　


2 Working principle

2. 1Interface with CODEC
　　CT8022 can be directly connected to one or two 8-bit A/μ rate codecs (A/D and D/A), or can be connected to a 16-bit linear codec. When used as an input/output signal, the specific parameters of the interface can be determined through host interface commands. When using two codecs, make sure they are of the same model. The CT8022 can provide a clock signal to the CODEC or use a common external clock signal with the codec. When CT8022 provides a clock signal to the CODEC, the clocks SCLK and FSYNC are divided by its internal clock through programming. The sampling frequency of CODEC is FSYNC. The internal clock relationship between SCLK, FSYNC and CT8022 is: 　　SCLK=CT8022’s internal clock/(N+1), where 3≤N≤31; 　　FSYNC=SCLK/(M+1), where 18≤M≤1023. 　　In the formula, M and N are frequency division factors, and the specific values ​​can be written with commands during initialization according to the sampling frequency. 2.2 External SRAM　　CT8022 requires at least 8k×8 SRAM to store the data required for operation. Basic operation and program codes are stored in on-chip ROM. The connection between CT8022 and external SRAM is shown in Figure 2. 　　BSEL is used to select the high/low byte. When the SRAM address line is 16 bits, this pin is not used.　　

　　







　　

　　

2.3 Host control interface
　　
　　The control of the CT8022 voice compression chip is carried out through the on-chip 8/16-bit control/status/data interface. This interface can be mapped into the internal host control address space, allowing the CT8022 to be used with inexpensive 8-bit or 16-bit microcontrollers. The controller operates the CT8022 by writing the control word to the control register, and obtains status information by reading the status register. Voice data can be recorded or played back by host access or DMA via a variable-depth receive or transmit buffer of up to 16 words. These control registers include hardware control register (HCS), hardware status register (HSR), software control register (SCR), software status register (SSR), auxiliary software control register (ASCR) and auxiliary software status register (ASSR), etc., and The buffer in the device operates the language data through the host read/write data buffer access port.
　　
　　CT8022 contains two 16-word (32-byte) data buffers, through which the host can send data to CT8022, and the host can also receive data from CT8022. Access rights to these two buffers are controlled by the CT8022, and the host can access them indirectly through two 16-bit host data buffer ports. Since the host data bus is 8 bits, the high/low byte should be accessed according to HSTAB0 selection, and the address required for access is generated by the address counter inside CT8022. The addresses of each register are listed in Table 1.
　　
　　HSTAB0 in the table is used to select the upper 8 bits or lower 8 bits of the 16-bit control word. When HSTAB0 is 0, the lower 8 bits are selected, and when it is 1, the upper 8 bits are selected; when accessing, the lower 8 bits are first followed by the upper 8 bits.

3 Working modes

　　The main working modes of CT8022 are: empty mode, playback (decompression) mode and recording (compression) mode.
　　
　　After power-on or reset, the host must put the chip into idle mode before other command operations can be performed. At this time, the transmit/receive buffer is empty and data from the CODEC will be ignored.
　　
　　In replay mode, the transmit register in CT8022 is activated, and the host should send compressed data to CT8022 to decompress it. When data is interrupted, CT8022 will repeatedly decompress the data in the sending register and send it to the CODEC until the host resends valid data.
　　
　　In the recording mode, the receiving register in the CT8022 is activated. The CT8022 compresses the data sent by the CODEC and sends it to the receiving register, and then the host takes away the data in the register. If the host fails to retrieve the data in the register in time, the data in the register will be replaced by the data in the next frame.
　　
　　When the system is in full-duplex mode, voice compression and decompression can be performed simultaneously.
　　
　　The codec loop mode of CT8022 is a test mode, which can be used to send the code stream sent from the CODEC directly back to the CODEC without compression.

4 Workflow

　　The host can control the CT8022 through the command-response protocol. CT8022 will generate a status response signal for each command issued to the host. Therefore, the host should read the response signal before issuing the next command. The host's control command to CT8022 is implemented by writing SCR. When the CT8022 is ready to receive commands, the CONTROLREADY bit in the HSR should be set. At this time, the host can only write commands to the SCR. CT8022 will generate the command response signal by writing SSR. The host can read status information from the SSR and clear the STATUSREADY bit only after the STATUSREADY bit in the HSR is valid. Since the control register of CT8022 is 16 bits and the host interface is 8 bits, when the host writes the control word, it should write the low byte first and then the high byte. 4.1 Initialization　　When using CT8022, it must be initialized first. The specific process is as follows: 　　(1) After the system is powered on or reset, the host accesses the HSR until the CONTROLREADY bit is valid. 　　(2) The host first writes the command 0000H to set CT8022 to empty mode to SCR. 　　(3) CT8022 generates a response and sets the STATUSREADY bit of HSR. 　　(4) When the host detects that the STATUSREADY bit is valid, it reads status information from the SSR. 　　(5) The host writes the CODEC configuration command to the SCR. 　　(6) CT8022 configures the interface with CODEC according to the configuration command, generates response information, and sets the STATUSREADY bit. 　　(7) When the host detects that the STATUSREADY bit is valid, it reads status information from the SSR. 4.2 Write control word　　After the initialization is completed, the host can write the control word to specify the specific working status of CT8022. 　　The following is related to ITU-G. The 723.1 compatible 6.3kbits/s compression algorithm is used as an example to illustrate the specific process of setting the CT8022 to the compression state (recording mode). Assume that CT8022 has been initialized and is in empty mode, and the CODEC interface complies with G. 723.1 requirements. The process is as follows: 　　(1) The host detects the CONTROLREADY bit of HSR. 　　(2) Set the rate to 6.3kbit/s by writing command word 5131H to SCR. 　　(3) CT8022 sends a response signal through SSR. 　　(4) The host detects the STATUSREADY bit of HSR, reads the SSR after detecting this bit, and automatically clears STATUSREADY. 　　(5) Write control word 5102H to SCR so that data can be automatically exchanged with the CT8022 internal register at the host read/write data buffer port. 　　(6) CT8022 responds to commands through SSR. 　　(7) The host detects the STATUSREADY bit of HSR, reads SSR after detection, and automatically clears STATUSREADY. 　　(8) The host writes the control word 1C03H to the SCR, indicating that the host will read data through the host receive data buffer access port. (9) CT8022 completes internal synchronization and generates a response. 　　(10) The host detects the STATUSREADY bit of HSR. After detection, it reads SSR and automatically clears STATUSREADY. (11) At this point, CT8022 is in recording mode. The data sent by CODEC can be compressed into a frame with a length of 30ms. Each compressed data frame is sent to the host by the CT8022 in the following two ways: the first is for the host to detect RXReady in the HSR and then wait for this bit to be set. The second is for the host to read 12 words of data from the host receive data buffer access port. 4.3 Stop operation　　If you want to stop recording, you can perform the following operations: 　　(1) Write the empty mode command word 0000H to SCR, or execute the stop recording command 5120H. 　　(2) CT8022 stops compressing data and clears the RXReady bit. 　　(3) CT8022 writes command response information to SSR. 　　(4) The host detects the STATUSREADY bit of HSR, reads SSR after detection, and automatically clears STATUSREADY. 　　


　　







 


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5 Application circuit

　　The block diagram of the voice compression application circuit composed of CT8022 and host is shown in Figure 3.