France's CEA-Leti announces "breakthrough" in three-layer integration of AI-embedded image sensors

At the ECTC 2024 conference in Denver, France, research institute CEA-Leti demonstrated a new process combining hybrid bonding and high-density through-silicon vias (TSVs) for embedding artificial intelligence (AI) in CMOS image sensors (CIS).

CEA-Leti scientists reported at ECTC 2024 a series of successes in three related projects that are key steps toward realizing a new generation of CMOS image sensors (CIS) that can use all image data to perceive the scene, understand the situation and intervene - capabilities that require AI embedded in the sensor.

The demand for smart sensors is growing rapidly as they enable high-performance imaging capabilities in smartphones, digital cameras, automobiles, and medical devices. This demand for enhanced image quality and functionality through embedded artificial intelligence presents manufacturers with the challenge of improving sensor performance without increasing device size.

“Stacking multiple chips to create 3D architectures, such as tri-layer imagers, has led to a paradigm shift in sensor design,” said Renan Bouis, lead author of the paper, “Backside Thinning Process Development for High-Density TSVs in Tri-Layer Integration.”

“Communication between different layers requires advanced interconnect technology, and hybrid bonding technology can meet this requirement because of its very fine pitch, in the micron or even submicron range,” he said. “High-density through-silicon vias (HD TSVs) have similar density and can transmit signals through the intermediate layers. Both technologies help to shorten the wire length, which is a key factor in improving the performance of 3D stacking architectures.”

The three projects apply the institute's previous research results, which used these technology modules to stack three 300 mm silicon wafers.

“This research introduces the key technological building blocks necessary to create 3D multilayer smart imagers that can address new applications requiring embedded AI,” said Eric Ollier, Project Manager at CEA-Leti and Head of the Smart Imager Project at IRT Nanoelec. The CEA-Leti Institute is a key partner of IRT Nanoelec.

“The combination of hybrid bonding and high-density through-silicon vias in CMOS image sensors can facilitate the integration of various components, such as image sensor arrays, signal processing circuits, and memory elements, with unparalleled precision and compactness,” said Stéphane Nicolas, lead author of the paper “3-Layer Fine-Pitch Cu-Cu Hybrid Bonding Demonstrator with High-Density TSVs for Advanced CMOS Image Sensor Applications,” which was selected as one of the conference’s highlight papers.

The project developed a three-layer test vehicle with two embedded Cu-Cu hybrid bonding interfaces, face-to-face (F2F) and face-to-face (F2B), and one wafer containing high-density TSVs.

Ollier said the test vehicle was an important milestone because it demonstrated not only the feasibility of each technology module, but also the feasibility of the integration process. “This project laid the foundation for demonstrating a fully functional three-layer smart CMOS image sensor with edge AI capable of solving high-performance semantic segmentation and object detection applications,” he said.

Last year, CEA-Leti scientists reported a double-stacked test chip that combined high-density through-silicon vias (TSVs) 10 microns high and 1 micron in diameter with highly controllable hybrid bonding technology, both assembled in an F2B configuration. The latest research results have shortened the high-density TSVs to 6 microns, thereby developing a double-stacked test chip that not only has low-dispersion electrical performance but also simplifies the manufacturing process.

“Compared to 1 micron x 10 micron high-density TSVs, our 1 micron x 6 micron high-density TSVs have better resistance and isolation performance, thanks to the optimized thinning process, which allows us to reduce the substrate thickness with good uniformity,” said researcher Stéphan Borel.

“The reduction in height reduces resistance by 40%, proportional to the reduction in length. At the same time, reducing the aspect ratio increases the step coverage of the isolation pad, thereby improving the withstand voltage performance,” he added.

“These new 3D multi-layer smart imagers that implement edge AI in the sensor itself will truly be a breakthrough in imaging, as edge AI will improve imager performance and enable many new applications,” Ollier explained.