In-depth understanding of automotive SoC: Overview of automotive SoC and AEC-Q100 automotive standards

SoC, system-level chip, automotive system-level SoC is mainly aimed at two areas, one is cockpit, the other is intelligent driving, and the boundary between the two is becoming increasingly blurred. With the evolution of automotive electronic architecture, gateway SoC has emerged, and the typical representative is NXP's S32G274A. Usually gateway SoC does not require too much computing power, but S32G274A has 4 Cortex-A53 cores, reaching the level of low-end cockpit.

Nvidia Orin internal framework diagram

Image source: Internet

Orin is a typical smart driving SoC, which includes storage management, peripherals, CPU, GPU and accelerator. CPU, GPU, AI accelerator and the bus or network on chip (NoC) connecting the subsystems are the core of SoC, so this series will be divided into four chapters to give you a deep understanding of automotive SoC. The directory is as follows:

System-on-Chip White Paper

Chapter 1

Definition and Introduction of Automotive SoC

1.1. Definition of Automotive SoC

1.2 SoC Design Process

1.3. AEC-Q100 for automotive certification

1.4 AEC-Q100 test process and description

1.5. Statistics on the computing power of common cockpit and intelligent driving SoCs at present and in the future

1.6. Automotive chip foundry

Chapter 2

CPU Microarchitecture

2.1、ARM architecture CPU

2.2 Modern Computer Computing Architecture

2.3 Von Neumann Architecture

2.4 Harvard Architecture

2.5 CPU Microarchitecture

2.6 Fixed-point and floating-point

2.7 Cache and TLB

2.8 Superscalar Computing

2.9 Super Pipeline

2.10 Out-of-order execution (OoOE)

2.11. Reorder Cache ROB

2.12 Branch Prediction

2.13 CISC and RISC

2.14 Micro-operation μ-op and macro-operation marco-op

2.15 Launch and Execution

2.16、Analysis of AMD Zen2 CPU Microarchitecture Used in Tesla Cockpit

2.17. The key to automotive functional safety: ARM's multi-core scheduling DSU

2.18 RISC-V

2.19. ARMHPC Dedicated Platform

2.20 FPGA

Chapter 3

GPU microarchitecture and examples

3.1 GPU Overview

3.2 GPU Physical Architecture

3.3 SIMD and SIMT

3.4. GPU CPU overhead, namely Draw Call driver overhead

3.5 GPU Graphics Processing Logic Pipeline

3.6 CUDA

3.7 ARMMALI GPU

3.8 ARMMALI-G710

Chapter 4

AI Accelerator

4.1. Machine Learning Basics

4.2 Basic concepts of deep learning

4.3. AI accelerator has the lowest threshold

4.4. Storage is the most important

4.5 Qualcomm AI100 Accelerator

4.6. The key to AI chips is packaging

Chapter 5

Interconnection between NoC and Die

5.1、ARM's on-chip bus

5.2. NoC (Network on Chip)

5.3 Why use NoC

5.4. Arteris, the leading supplier of NoC IP for automotive SoCs

5.5. Chiplet

5.6 Chiplet interface standards

5.7 CCIX Cache Coherence Alliance

5.8 CXL Alliance

Automotive SoC Definition

Generally speaking, any MCU with slightly stronger computing power (above 2K DMIPS) in the automotive field can be considered a SoC.

An average of 23 SoCs per vehicle

Image credit: Arteris

The above picture is the IPO material of SoC IP supplier Arteris. Arteris believes that there are 23 SoCs in each car on average.

A typical SoC structure includes the following parts:

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• At least one microprocessor (MPU) or digital signal processor (DSP), but there can also be multiple processor cores;

• 
  

• The memory may be one or more of RAM, ROM, EEPROM and flash memory;

• 
  

• Oscillator and phase-locked loop circuit for providing time pulse signal;

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• Peripherals consisting of counters and timers, power supply circuits;

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• Connection interfaces of different standards, such as USB, FireWire, Ethernet, Universal Asynchronous Receiver/Transmitter and Serial Peripheral Interface, etc.

• 
  

• Voltage conditioning circuits and voltage regulators.

SoC Design Flow

Image source: Synopsys

A complete system-level chip consists of two parts: hardware and software. The software is used to control the microcontroller, microprocessor or digital signal processor core of the hardware part, as well as external devices and interfaces. The design process of the system-level chip is mainly the collaborative design of its hardware and software.

As the integration of system-level chips becomes higher and higher, design engineers must adopt reusable design ideas as much as possible. Most SoCs today use predefined IP cores (including soft cores, hard cores, and solid cores) to complete rapid design in a reusable design manner. In software development, the protocol stack is an important concept that is used to drive industry standard interfaces such as USB. In hardware design, designers usually use EDA tools to connect already designed (or purchased) IP cores together and integrate various sub-functional modules under an integrated development environment (IDE).

Before the chip design is sent to the wafer fab for tape-out, designers will verify its logical functions in different ways. Simulation and verification are the most complex and time-consuming parts of the SoC design process, accounting for about 50% to 80% of the entire chip development cycle. The use of advanced design and simulation verification methods has become the key to the success of SoC design.

AEC-Q100 automotive certification

The Automotive Electronics Council (AEC) was established by Chrysler, Ford and General Motors to develop common quality standards for electrical components. The first version of the AEC standard was launched in 1994, with 100 for integrated circuits, 101 for discrete components, 102 for optoelectronic components, 104 for MCM modules, and 200 for passive components.

AEC-Q100 Standard Status

Image source: MPS

AEC-Q100 is the most widely used and basic automotive-grade standard and is almost a mandatory standard. Functional safety is not a mandatory standard but only a recommended standard.

AEC-Q100 ambient operating temperature range standard

Image source: AEC Council

Temperature range is one of the core criteria of AEC-Q100.

AEC-Q100 key test categories include:

1) Accelerated Environment Stress

2) Accelerate LifetimeSimulation

3) Packaging/Assembly

4) Die Fabrication

5) Electrical Verification

6) Defect Screening

7) Cavity Package Integrity

AEC-Q100 test process and description

AEC-Q100 Certification Process

Image source: AEC Council

AEC-Q100 Environmental Stress Test

Image source: AEC Council

AEC-Q100 Accelerated Lifetime Simulation Test

Image source: AEC Council

AEC-Q100 Package Integrity Testing

Image source: AEC Council

The most interesting one is D. There is no test standard and method. It is mainly for testing in the field of chip manufacturing. It may be because the field of chip manufacturing changes too fast or due to other factors. Therefore, AEC-Q100 only proposes test items, namely electromigration (EM), dielectric breakdown TDDB, hot carrier injection HCI, negative bias temperature instability NBTI, and pressure migration SM. The test standards and methods are blank. The AEC committee adds that the data, test method, calculations and internal criteria should be available to the user upon request for new technologies. It means that users can do it as they please.

AEC-Q100 electrical characteristics test

Image source: AEC Council

AEC-Q100 Group F and G testing

Image source: AEC Council