Design of EnDat encoder data acquisition follow-up circuit based on FPGA

Abstract: With the development of integrated circuit technology, FPGA has been widely used in high-speed digital signal transmission and data processing due to its small size, high speed, low power consumption, flexible design, easy system integration, expansion and upgrading. EnDat data interface is a bidirectional digital interface suitable for encoders. EnDat can transmit the position value of the encoder, and can also transmit or update the information stored in the encoder or save new information. This paper introduces the characteristics, functions, timing and data transmission, OEM data storage, and subsequent circuit design scheme of encoder data acquisition of EnDat interface, and the design of FPGA encoder interface is used for communication between encoder and DSP processor.

0 Introduction

The EnDat interface is a digital, full-duplex synchronous serial data transmission protocol designed by HEIDENHAIN specifically for encoders. It has the advantages of fast transmission speed, powerful functions, simple wiring, and strong anti-interference ability. It is a universal interface for encoder and grating ruler data transmission. Due to the use of serial transmission, only four signal lines are required. Under the clock excitation of subsequent electronic equipment, data information is transmitted synchronously. The data type (position value, parameter, diagnostic information, etc.) is determined by the mode instruction selection sent to the encoder by the subsequent electronic equipment. The encoder uses natural binary, cyclic binary (Gray code) or PRC code to perform photoelectric conversion on the physical engraved lines on the code disk, convert the rotation angle of the connected shaft into a corresponding electrical pulse sequence and output it in digital quantity. It has the advantages of small size, high precision, digital interface and absolute positioning, and is widely used in many fields such as turntables, robots, CNC machine tools and high-precision servo systems.

1 Introduction to EnDat Interface

1.1 Characteristics of EnDat interface

(1) High performance and low cost: Universal interface suitable for all incremental and absolute encoders, more economical power consumption, small size and compact connection, fast system configuration, zero point can float according to the offset value.

(2) Better signal quality: The special optimization inside the encoder improves the system accuracy and provides better contour accuracy for the CNC system.

(3) Better practicality: automatic system configuration function; digital signals improve system reliability; monitoring and diagnostic information is beneficial to system safety; redundant code verification is beneficial to reliable signal transmission.

(4) Improved system security: two independent position information and error information bits, data checksum and response.

(5) Suitable for advanced technology development: (high resolution, short control cycle, fastest 16 M clock, safety design concept) Suitable for direct drive technology.

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1.2 EnDa2.2 encoder performance improvement

(1) The transmission position value and additional information can be transmitted simultaneously: the type of additional information can be selected by the storage address selection code.

(2) The encoder data storage area includes encoder manufacturer parameters, OEM manufacturer parameters, operating parameters, and operating status, which facilitates system parameter configuration.

(3) EnDa2.2 encoder realizes full digital transmission. The incremental signal processing is completed inside the encoder (built-in 14-bit subdivision), which improves the quality and reliability of signal transmission and can achieve higher resolution.

(4) Monitoring and diagnostic functions. Alarm conditions include: light source failure, insufficient signal amplitude, position calculation error, operating voltage too low or too high, excessive current consumption, etc.; warning signals are provided when some limit values ​​of the encoder are approached or exceeded.

(5) Wider voltage range (3.6-14 V) and transmission rate (16 M).

1.3 Timing and OEM Data Storage

A data packet is sent during each frame of synchronous data transmission. The transmission cycle starts with the first falling edge of the clock. The measured value is saved and the position value is calculated. After two clock pulses (2T), the subsequent electronic device sends the mode command "encoder transmits position value" (with or without additional information). After the absolute position value is calculated (see Figure 2), the encoder transmits data to the subsequent electronic device starting from the start bit. The subsequent error bits F1 and F2 (only in EnDa2.2 instructions) are group signals for all monitoring functions and fault monitoring services. Their generation is independent of each other and is used to indicate encoder faults that may lead to incorrect position information. The exact cause of the fault is saved in the "operating status" storage area and can be queried by subsequent electronic devices.

Starting from the least significant bit, the absolute position value is transmitted, and the length of the data is determined by the type of encoder used. The number of clock pulses required to transmit the position value is saved in the parameters of the encoder manufacturer. The transmission of the position value data ends with a cyclic redundancy check code.

If the position value carries additional information, the additional information 1 and 2 follow the position value, and they also end with a CRC (see Figure 3). The content of the additional information is determined by the selected address of the storage area and then transmitted in the subsequent sampling cycle. This information is transmitted in subsequent transmissions until a new storage area is selected. At the end of the data word, the clock signal must be set to a high level. After 10 to 30 μs or 1.25 to 3.75 μs (EnDat programmable recovery time tm), the data line returns to a low level, and then new data transmission can begin under a new clock signal.

At the same time, the encoder provides different storage areas for parameters, which can be read by subsequent electronic devices. These areas can be written by the encoder manufacturer, OEM manufacturers or even end users. Some specific areas can be write-protected. Different series of encoders support different OEM storage areas and different address ranges. Therefore, each encoder must read the allocation information of the OEM storage area. For this reason, subsequent electronic circuits should be programmed based on relative addresses instead of absolute addresses. [page]

2 Circuit design of subsequent electronic devices of EnDat interface

TMS320F2812 is used as the controller in the fully digital AC servo system to realize the functions of position loop, speed loop and current loop as well as SVPWM, voltage and current sampling, etc. In addition, the Cyclone series FPGA of Altera, model EPlC6Q240C8, is used to realize the functions of encoder interface and decoding logic, etc. At the same time, a 128B dual-port RAM is implemented inside the FPGA to realize data transmission with the DSP through the bus. The functional block diagram is shown in Figure 4.

The FPGA is divided into five parts: clock generation module, transmission module, receiving module, dual-port RAM module, and transmission enable module. First, the clock generation module generates a square wave signal with a period of 0.5μs, named CLOCK, which is used as the communication synchronization clock signal. At each rising edge of CLOCK, the counting variable COUNT is incremented by 1, and the initial value of the variable COUNT is 0. When the transmission enable module detects that the value of COUNT is 3, it means that the encoder has saved the position value. The transmission enable module enables the SENT_EN signal, and the transmission module starts to send 6-bit mode instructions. When the value of COUNT is detected to be 9, COUNT stops counting at each rising edge of the clock, stops sending data, and enables the receiving enable signal RECEIVE_EN, thereby enabling the receiving module. The receiving module starts to detect the rising edge of the data input signal. Once the rising edge arrives, it means that the data start bit s is received. COUNT is started to count at each clock rising edge. The position value is saved at the rising edge of each clock signal until the value of COUNT is 39. Then the receiving module stops receiving data and writes the position value to be saved to the A port of the dual-port RAM module, thus ending the communication process between the FPGA and the encoder. Since the communication time is strictly fixed each time, the system clock is set to 2MHz. The FPGA is the caller. When the falling edge of the clock arrives, it takes 2 clock cycles for the encoder to save the position value. It takes 6 clock cycles to send the "request data" control word of 6 bits "000111" to the encoder. It takes 31 clock cycles for the encoder to send 1 start bit, 2 "error bits", 23 position values ​​and 5 CRC check bits to the FPCA, a total of 39 clock cycles, so each communication takes 19.5μs, and the specific data to be transmitted at each moment is also strictly determined. Therefore, the design method based on the time base is adopted (see Figure 5).

A 128 B dual-port RAM space is implemented inside the FPGA. Port A has 8-bit data lines and 7-bit address lines for communicating with the encoder. Port B has 16-bit data lines and 7-bit address lines for communicating with the DSP. Because TMS320F2812 is a 16-bit DSP, data transmission with the RAM in the FPGA is extremely convenient. The DSP sends a valid "BEGIN" signal in each current loop cycle. After 19.5μs, the encoder signal receiving module stores the received data in port A of the dual-port RAM inside the FPGA and arranges it in sequence into the form of 16-bit data. Then it sends an "END" signal to the DSP, indicating the end of a communication. After receiving the interrupt, the DSP reads the data from port B of the dual-port RAM of the FPGA to complete a communication. [page]

The FPGA is developed using the ISE integrated environment of XILINX, and the hardware description language is Verilog HDL. Figure 6 is a program flow chart.

3 Conclusion

This paper designs an FPGA-based encoder interface for communication between the encoder and the servo drive DSP processor, and has error correction functions such as CRC check. This paper gives the hardware connection and FPGA program design process, which can realize the accurate reading of the magnetic pole position of the permanent magnet synchronous AC motor.