Testing of Gigabit switching backplanes

    Abstract: This article introduces the test system of Gigabit switching backplane. The system consists of a backplane, switching card, line card and control card. It can detect the switching function and transmission function of the switching backplane. After actual operation and testing, it was proved that the switching capability of the test system reached the level of Cisco2008 router.

    Keywords: switching backplane test system gigabit technology

With the rapid development of the Internet/Intranet, the rapid increase of network traffic has caused unprecedented changes in the existing data transmission structure, traffic content, mode and composition structure. The form of data transmission is gradually shifting from connection-oriented services to connectionless and dynamic IP services. For public carriers, IP is becoming more and more important in applications.

    Changes in network services and traffic make the optimization of the network's core switching structure, routers, and IP backbone increasingly important. Routers play an important role in network switching technology. In particular, the performance of core routers determines the throughput of the network. The IP data packet switching technology implemented by hardware mechanism makes the performance of modern routers far exceed that of traditional routers that implement data packet forwarding by software mechanism. The core technology of data packet switching lies in the scheduling algorithm of high-speed switching backplane and high-speed interconnection and transmission technology. The testing of switching backplanes also focuses on these two points: testing of scheduling algorithms and testing of high-speed backplane transmission performance.

The performance indicators of the switching backplane composed of the system

    are: 8 ports with input/output functions; the serial data transmission rate of each port is 1.25Gbps. Through 8×8 switching switches, the cumulative switching rate of the entire backplane reaches 10Gbps (8×1.25Gbps); fixed-length packets (cells) are exchanged on the backplane; data packet transmission includes unicast and multicast. The system works in synchronous mode and the operating frequency is 125MHz.

    The test system includes switching cards, line cards, control cards and backplanes. The function of the switching card is to implement the scheduling algorithm and configure the data connection according to the scheduling results; the line card cooperates with the switching card to complete the scheduling, realize the switching function of the system, and perform data transmission according to the scheduling results to check the backplane transmission bit error rate; the control card It manages the system and generates control signals and some command parameters to control the operating mode of the system; the backplane is the medium for data and signal transmission, which determines the data transmission performance of the system.

The system structure and design implementation

    are divided according to functions. The system can be divided into: scheduling module, transmission module, clock module and control module. The design and implementation of these modules are introduced below.

    The scheduling algorithm used in the high-level algorithm implementation

    system is the ESLIP algorithm. The scheduler is implemented on the central switching card, and the line card cooperates with the switching card to implement the scheduling function. Each line card stores a set of random numbers, which represent the information of newly arriving cells in each time slot (cell transmission cycle). The line card determines the next time based on this information and the scheduling results sent by the switching card. The switching card collects the scheduling requests sent by each line card and generates the scheduling results and crossbar switch configuration information. The structure is shown in Figure 1:

    data transmission and error detection

    end at each time slot, the switching card determines the configuration of the crossbar switch based on the scheduling results, and the line card determines the data to be sent and received based on the scheduling results. When the system is initialized, the DSP on each line card writes the data to be sent into the SRAM; after the transmission starts, the sending module sends data to the sending memory according to the scheduling results, and the receiving module also writes the data into the receiving memory according to the scheduling results, sending in parallel. The data is converted into 1.25Gbps serial data through the gigabit transceiver, reaches the destination port through the backplane → crossbar switch → backplane, and then is written into the receiving memory through the serial/parallel conversion of the transceiver; when the receiving device on the line card After the memory is full, it no longer receives data and sends an interrupt request to the DSP, and the DSP begins to detect bit errors. as shown in picture 2.

    The clock module

    system works in synchronous mode, and all clocks are generated by a clock source on the switching card and distributed to each line card.

    The 16MHz crystal oscillator generates a clock signal, which is locked at 125MHz through a phase-locked loop, and then driven by a 1:8 clock driver and transmitted to each line card through the backplane. The line card receives and drives the scheduling module and control module, as well as the reference clock that serves as the gigabit transceiver. In order to ensure synchronization with the data, the clock used by the receiving module is the clock recovered by the transceiver from the serial received data.

    The control module

    control card controls the operating mode of the system. At the beginning of each detection, the control card sends a system reset signal and sends commands and parameters to each line card for controlling data types and scheduling information types. The line card performs on-board initialization based on these commands and parameters. After the initialization is completed, the control card sends a start signal and starts data transmission. After detecting that the receiving memory of all line cards is full, one transmission ends, and the control card reads out the bit error rate of each line card and starts a new round of transmission. The system workflow is shown in Figure 3:

Conclusion

    In system design, in order to improve system performance as much as possible and reduce design complexity, on the one hand, a large number of programmable logic chips (FPGA and EPLD) are used to make full use of their internal resources. Use its simulation tools as much as possible to verify the correctness of the design, simplify the design and save costs; on the other hand, use high-performance integrated chips, such as the S2064 gigabit transceiver and S2016 crossbar switch produced by AMCC, to ensure the accuracy of the design Correctness and reliability. Moreover, signal integrity simulation tools are fully utilized in the design phase for simulation analysis, especially for high-speed signals. The design of backplane wiring, gigabit transceiver design, connector selection and design, etc. have all been fully simulated and demonstrated. These works provide sufficient basis for system design.

    Actual operation and testing showed that the system correctly implemented the scheduling algorithm and tested the switching performance of the system; it achieved high-speed data transmission and switching at a single-line 1.25Gbps rate, with a bit error rate of less than 10e-14, and tested the signal on the backplane. Transmission quality. The system's switching performance and transmission capabilities have reached the level of the Cisco 12008 router.