Application of FPGA in digital frequency division multiplex subcarrier demodulator

    Abstract: A design scheme for a subcarrier demodulator for a digital frequency division multiplex telemetry system based on FPGA is proposed. It discusses in detail how to use the characteristics of FPGA to solve the demodulation problem of multi-channel FM signals. This kind of demodulator can be easily combined with a computer to form a digital FM-FM telemetry data processing system to adapt to the development needs of modern telemetry technology.

    Keywords: FPGA telemetry time division multiplexing demodulator

With the rapid development of large-scale integrated circuit technology and microcomputer technology, computerization has become the direction and feature of the development of telemetry technology. Traditional analog frequency division multiplex telemetry systems are increasingly unable to adapt to the development of modern telemetry technology. Because it has the following fatal shortcomings: (1) The analog signal output by demodulation cannot be directly processed and analyzed by the computer; (2) Once the system parameters are set, they cannot be changed, and the system flexibility is poor. In order to overcome the above shortcomings, it is necessary to fundamentally change the analog frequency division multiplex telemetry system and develop a new digital frequency division multiplex subcarrier demodulator.

Fortunately, the rapid development of digital signal processing technology and large-scale integrated circuit technology has provided us with new ideas and methods for designing digital frequency division multiplex subcarrier demodulators. In recent years, field programmable gate arrays (FPGAs) have been widely used in the design of digital systems due to their advantages such as high integration, fast processing speed, and high execution efficiency [1]. The digital frequency division multiplex subcarrier demodulator mentioned in this article is implemented using FPGA technology.

1 Overall design plan

The designed subcarrier demodulator of the digital frequency division multiplex telemetry system is ITIG-CBW-E standard, that is, the channel center frequencies are 128, 256, 384, 512, 640 and 768kHz respectively, the frequency offset is 32kHz, and the modulation signal frequency The range is 100Hz~25kHz.

1.1 System composition

This digital frequency division multiplex subcarrier demodulator applies digital signal processing technology and the idea of ​​spectrum migration to first digitize the analog FM signal and then digitally demodulate it. The demodulated output is a digital signal, which can be directly stored and analyzed by digital equipment. In addition, the digital signal can also be reconstructed analogously to restore the original analog signal. Its composition block diagram is shown in Figure 1.

As can be seen from Figure 1, the digital frequency division multiplex carrier demodulator is mainly composed of the analog front end, the digital demodulator and the third part of the analog reconstruction part. Among them, the analog front-end includes ACC circuit, anti-aliasing filter and A/D converter.

As an interface circuit between the analog part and the digital part, the analog front-end mainly completes the preprocessing and A/D conversion of multi-channel FM signals. The analog reconstruction part includes D/A converter and smoothing filter. It converts the demodulated digital signal into an analog signal. and amplified to the desired level.

The digital demodulator is the heart of the system. It consists of three parts: digital shunt filter, digital frequency discriminator and digital low-pass filter. It will complete the tasks of branch filtering and demodulation of multi-channel FM signals. Figure 2 shows the mathematical model of a single-channel digital demodulator.

As can be seen from Figure 2, we do not use a digital phase-locked loop, but use a digital signal processing (DSP) algorithm to achieve demodulation. This solution is more suitable to be implemented with FPGA.

1.2 Hardware circuit design

In order to facilitate debugging, when designing the hardware circuit, the digital demodulator, A/D and D/A are placed on different circuit boards and connected through double row plugs. The A/D converter is selected based on the sampling frequency and data width of the digital demodulator. Since the sampling frequency of the digital demodulator is 2.56kHz and the data bit width is 8 bits, the 8-bit high-speed analog-to-digital converter TLC5510, which is easy to debug, was selected. The D/A converter uses Maxim's MX7545. The digital demodulator uses Altera's FLEX10K series devices. When using MAX+plusⅡ for hardware simulation, a single digital demodulator requires a total of three FLEX10K50s, and its utilization rate can reach more than 75%. If the same method is repeatedly used to demodulate multi-channel signals, the hardware resources will be doubled. Obviously, this is uneconomical and unfeasible. Therefore, how to complete the demodulation of multi-channel signals without increasing or increasing the scale of system hardware has become a key issue to be solved during the design process.

2 Key technologies

In order to complete the demodulation task of multi-channel signals while saving system resources as much as possible, the time division multiplexing method is adopted. Using FPGA to implement a digital demodulator has the conditions for time division multiplexing.

On the one hand, the FPGA used can process data at a speed of up to 100MSPS, and the sampling rate of this system is 2.56MHz, which means the processing speed is required to be 2.56MSPS. Therefore, in theory, it is possible to use it to process more than 30 signals at the same time. of. Considering that the actual system cannot work at the maximum processing speed, assuming that it can only reach 1/3 of the maximum speed, after using time division multiplexing, at least 10 or more signals can be processed simultaneously.

On the other hand, since each branch filter (including the in-phase branch and the quadrature branch) uses a 64th-order FIR low-pass filter, its bandwidth, transition band bandwidth and stopband attenuation are exactly the same, that is to say, the impulse The response is exactly the same, so the vector multipliers that make up the FIR filter can be reused. Each output low-pass filter also has the same circuit structure. In principle, it is exactly the same as the shunt filter, so here we only take the shunt filter as an example for discussion. The FIR filter is mainly composed of a shift register, an adder and a vector multiplier [2], of which vector multiplication takes up most of the hardware resources in the FIR filter. Therefore, saving vector multipliers saves system resources. It can be seen that the essence of time division multiplexing refers to the time division multiplexing of vector multipliers.

The following is an example of how to implement time division multiplexing.

For the convenience of discussion, it is assumed that the order of the FIR filter is 8th order, and the number of time-division multiplexing channels k=2. Assume that the impulse response of the FIR filter is h(n), the first input signal is x1(n), the second input signal is x2(n), and the operating frequency of the filter is 2 times the input data rate. The two signals pass through the multiplexer to form a combined signal, the timing of which is shown in Figure 3.

It can be seen from Figure 3 that the combined signal output by the multiplexer actually interleaves the first signal and the second signal. The first signal appears at odd times and the second signal appears at even times. Signal. In order for the same signal to be output from the shift adder to the vector multiplier at the same time, it must be ensured that the signals output by the shift adder at odd-numbered moments are all the first-channel signals, and that the signals output at even-numbered moments are all the second-channel signals. Signal. In addition, it is necessary to ensure that both channels of data can be shifted sequentially under the control of the clock. In order to meet the above conditions, a two-channel signal multiplexing FIR filter is designed, and its structural block diagram is shown in Figure 4.

This filter only adds 8 shift registers [3] based on the 8th-order FIR filter. It is these 8 shift registers that allow the vector multiplier to cache the second signal when calculating the first signal; When the next time comes, the sum signal is output to the vector multiplier. In this way, simultaneous filtering of two signals is completed. The filtered signals are still output in interleaved form, and a splitter can be used to separate them.

Similarly, if k-channel filtering is performed at the same time, the number of shift registers in the filter will be k times the number of shift registers in a single-channel FIR filter. That is, assuming that the order of the FIR filter is N, the number of shift registers required for a single-channel filter is N, and the number of shift registers required for a K-channel filter is k·N.

In addition, it is worth noting that after using the time division multiplexing method, the entire system works at different clock frequencies. Assume that the system sampling frequency is fs, and k channels of signals are processed simultaneously after time division multiplexing. Then the clock frequency of the non-time division multiplexing part is fs, and the clock frequency of the time division multiplexing part is k·fs. In order for the system to work normally, it is necessary to Add clock and control circuits to the system to control the clock and synchronization of the system. Figure 5 shows the time division multiplexing block diagram of the shunt filter.

Using MAX+plusⅡ to compile the AHDL source code of the two-channel signal multiplexing filter, it was found that the two-channel signal multiplexing filter uses less than 20% of the hardware resources of the single-channel filter than the single-channel filter. Therefore, using time division multiplexing method achieves the expected goal.

The advantage of this FPGA-based digital demodulator is that it is easy to combine with a computer to form a digital FM-FM telemetry data processing system. On the one hand, the telemetry data can be transmitted to the computer for storage, analysis and display; on the other hand, the computer can also load different programs into the digital demodulator to change the parameter settings of the demodulator to make it suitable for IRIG. All standards.

However, this digital demodulator still has its shortcomings, that is, the calculation accuracy is not high enough because it is difficult to perform floating point calculations using FPGA. If the filter is implemented with FPGA, the data width is 12 bits, and the frequency discriminator is implemented with DSP, using floating point operations, the system accuracy will definitely be improved, but at the cost of increased system complexity.