Phase noise measurement circuit

    Measuring the phase noise of a variable frequency oscillator or synthesizer uses an expensive spectrum analyzer. For specific measurements at a fixed frequency of 455kHz, cheaper methods are available.

    The circuit in this article uses a phase error to control the current modulator, and locks the low-noise reference oscillator to the signal under test to implement a PLL. The reactance modulator uses a low pinch-off voltage junction FET of about 1.4V.

    Bipolar transistors in Clapp configuration form the reference oscillator. The coupling of the transistor to the oscillator circuit is very weak, so the load placed on it is very small.

    The following buffer oscillator circuit suppresses any harmonics and provides a 90° phase shift. The output of the quadrature demodulator is dc coupled to the input of the oscilloscope (used in X/Y mode).

    Phase noise deviation is displayed directly on the oscilloscope, with a full circle representing ±180° of peak phase noise. The phase deviation probability distribution is an intermediate form between the Rayleigh and Gaussian normal distributions (see 'Noise', Electronics World, Feb. 1998, pp. 146-151).

    The -3dB roll-off frequency is 3Hz, which is determined by R1 and C1. This parameter is the main point of the design. The receiver or transceiver under test must provide a 455kHz output. Trimming capacitor C2 must be adjusted so that the rms voltage on the gate of Tr1 cannot exceed 100mV. The performance of the completed circuit was evaluated using a FET crystal oscillator.