Application of AWG in High-Speed ​​Serial Signal Reception Performance Test (Part 2)

1. SATAG1/G2/G3 consistency test:
 
         Currently, SATA Workgroup has released the consistency test specifications and implementation methods for the transmitter, cable and receiver. The jitter tolerance consistency test of the receiver of SATA Gen I, Gen II GIII requires the DUT to comply with the built-in self-test (BIST-Built-In Self Test) instructions using a specific frame information structure (FIS-Frame Information Structure). When receiving a specific sequence of BIST-L (loopback) frames, the serial transceiver (including transmitter, receiver and SERDES) unit is designed to enter a dedicated loopback mode. When the device is in this mode, the test instrument (signal source) sends a jitter-containing signal to the receiver of the DUT, and then the transmitter of the DUT will respond correctly to the received signal. Finally, the error frame detector (Frame error detector) detects whether the data output by the DUT's transmitter is correct. Alternatively, the jitter amplitude injected by the signal source can be gradually increased until the Frame error detector detects the appearance of an error frame. The jitter amplitude obtained at this time is the jitter tolerance value of the receiver. This approach is necessary because the entire transceiver is typically implemented on-chip, so internal signal paths cannot be accessed for probing. Traditionally, BIST-L commands have been provided by an external PC running a dedicated application software to force the DUT into loopback mode. Unfortunately, once the BIST signal source is disconnected, most transceivers automatically exit loopback mode and return to normal operation, making it impossible to continue testing! A common solution to this challenge is to deliver the BIST-L command to the DUT through a power combiner. The other output of the power combiner is connected to the signal generator that provides the test data stream, as shown in Figure 11. By using a power combiner in the test circuit, the data generator can begin sending test data to the DUT when loopback mode is activated, without requiring disconnection. Power combiners are a viable solution, but they have their drawbacks. Obviously, they increase complexity and the chance of connection errors, poor electrical contacts, and other mechanical problems. They also require calibration of all input sources to ensure that jitter components are properly introduced. On top of that, power combiners can attenuate the data signal voltage by up to 50%. This problem can usually be solved by increasing the output amplitude of the data generator, but it will limit the performance of the instrument; in addition, increasing the amplitude will inevitably introduce noise and distortion.
 
            Figure 11 Method of implementing jitter tolerance test on SATA receiver with digital signal source
 
         But if the AWG direct synthesis method is adopted, the instrument can send BIST-FIS instructions instead of the PC. In other words, the output of the AWG is a continuous data stream, in which the BIST-FIS command comes first, followed by the jittered data, and there will be no interruption in between. It does not require a power synthesizer or a PC running BIST-FIS software. Figure 12 is an AWG-based jitter tolerance test system consisting of only two instruments: one instrument generates the input signal and one instrument reads the output. The AWG's memory does not distinguish between BIST-FIS data, out-of-band signals, clock signals, or actual data streams and their abnormal events.
 
 
                 Figure 12 Direct digital synthesis signal source to achieve SATA jitter tolerance test method
 
2. Displayport consistency test
 
         In the jitter tolerance test of the receiver of the display port Compliance Test Specification Version1, the signal source is required to provide signals containing different jitter frequencies, jitter amplitudes and jitter components, which are input to the receiving end of the sink, and then the bit error rate of the sink is observed to test the PLL performance of the receiving end, as shown in Table 1. This is a challenge for traditional digital signal sources. Please see the solution of traditional digital signal sources in the figure. In order to synthesize complex jitter components, an additional noise signal generator and vector signal generator are required, and both need to be synthesized with a power divider to inject jitter into the digital signal source. The unique advantage of the direct synthesis signal source implementation method in Figure 14 is that it only needs to press one key to output the synthesized signal. These signals include sine, ISI, Rj, Pj jitter, pre-emphasis, balance, jump time and amplitude control. The connection is simple and the consistency and repeatability of the test are very high.
 
 
         Table 1 Jitter characteristics of input signals required in DisplayPort Sink jitter tolerance test specification
 
 
      Figure 13 Method for implementing jitter tolerance test of DisplayPort receiver using digital signal source
 
 
              Figure 14 Method for implementing jitter tolerance test of DisplayPort using direct digital synthesis signal source
 
3. HDMI consistency test.
        
         In the HDMI CTS1.4 specification, it is required that in addition to adding two frequencies of jitter in the Sink jitter tolerance test, TTC (transition time converter) and Cable emulator should also be added to ensure that the rise time and jitter components of the signal meet the specification requirements. The digital signal source is implemented using the method shown in Figure 15.
 
For TTC, different TTCs are required for different test frequencies.
They are: 74.25MHz/450ps; 148.5MHz/220ps; 165MHz/200ps; 222.75MHz/150ps; 340MHz/60ps
For Cable emulator, it is also required to use 5 cable emulators with different characteristics at different test frequencies. See Table 2 below.
 

Typical(MHz)	1st Cable Emulator	2nd Cable Emulator
27	Type1 Cat1+Cat2	Type2 27MHz
74.25	Type1 Cat1	Type2 75MHz
148.5	Type1 Cat2	Type3
222.75	Type1 Cat2	Type3
340	Type1 Cat2	Type3

 
For the Automotive Type E interface, two new types of Cable Emulators have been added and currently only support 74.25MHz. In the future, 148.5 and higher resolutions will require more Cable Emulators.

	Automotive Cable Emulator
27	Type 1 Automotive1+Automotive2
74.25	Type 1 Automotive1

 
Table 2 Types of Cable emulators required for HDMI Sink jitter tolerance test
 
         According to the specification, the test of Sink requires testing its performance at different clock frequencies, which will lead to frequent replacement of different TTCs and Cable emulators during the test. In addition to spending a lot of time, it will also lead to test differences caused by factors such as poor signal contact caused by frequent changes in connections. In addition, since Cable emulators and TTCs are expensive, and some types of Cable emulators are not sold by manufacturers, customers cannot buy them or need to spend a lot of extra money. If
 
         the signal is generated by directly synthesizing the signal, there is no need for additional TTCs and Cable emulators, and the characteristics of TTCs and Cable emulators can be simulated by AWG. As shown in Figure 16, the signal output by the AWG includes the specified jitter frequency and jitter amplitude, and the jitter and attenuation effects brought by TTCs and Cable emulators are added. In other words, the output of the AWG can be directly connected to the input of the DUT for testing without the need for complex accessory connections.
 
 
Figure 15 Method for implementing jitter tolerance test of HDMI receiver using digital signal source
 
 

Figure 16 Method for implementing jitter tolerance test of HDMI using direct digital synthesis signal source
 
 
4. USB 3.0 compliance test:
When performing jitter tolerance test, in addition to the reference clock of the transmitter and receiver must be added SSC, the pre-emphasis level is set to -3dB, the voltage is set to 0.75V, the DUT is set to loopback mode, and the test needs to inject deterministic jitter Dj (the change of deterministic jitter is through each injection change of Sj) and random jitter (Rj remains unchanged). The requirements for injecting jitter at the test point TP1 are as follows

Frequency	SJ	RJ
500kHz	400ps	2.42ps
1MHz	200ps	2.42ps
2MHz	100ps	2.42ps
4.9MHz	40ps	2.42ps
50MHz	40ps	2.42ps

The AWG7000B series with direct synthesis technology can directly create jitter patterns and pre-emphasis, replacing the previous solution that required the use of three instruments including BERT, noise generator and jitter generator, greatly improving the accuracy and efficiency of the test. Because it can generate damaged waveforms with higher test requirements, even if the test specifications are updated and improved in the future, it can fully meet the requirements.
Tektronix's AWG7122B can easily generate various damaged waveforms through SerialXpress, adding PJ, RJ, ISI and pre-emphasis; it can easily perform Reference Cable Emulation; simulate user-defined cables, and users can determine the maximum length of cables that their DUT can work properly; generate user-defined SSC profiles (for example, the test needs to simulate SSC Noise and df/dt changes); inject Sj without considering hardware limitations, and generate it completely through software; support complex pre-emphasis function requirements; directly synthesize the corresponding waveform for LFPS testing.
 The figure below is Agilent's USB 3.0 configuration scheme, which requires multiple instruments to be combined. [page]
 
5. Wireless USB test:
Since wireless USB uses MB-OFDM modulation, the highest frequency is 10.296GHz. General digital signal sources cannot directly achieve this modulation output. It must be combined with baseband signal source and modulation signal source to output. AWG equipment can directly output by direct synthesis. AWG can directly simulate baseband, digital intermediate frequency and RF signals.