About High-Speed ​​Multi-Channel Virtual Logic Analyzer

　　The test object of the logic analyzer is the digital information in the digital system [1]. In order to meet the detection requirements of the modern data domain, the logic analyzer should have a high sampling rate and sufficient input channels. Based on the concept of virtual instrument, this paper mainly discusses the design principle and method of a 400MHz/102-channel logic analyzer based on PC586, focusing on the system control circuit design and system software design.

　　2 Virtual Logic Analyzer Architecture

　　Figure 1 is a block diagram of the overall structure of the 400MHz/102-channel virtual logic analyzer control and acquisition system in a PC environment, which mainly includes data acquisition, probes, trigger tracking, timing conversion and generation, and test interfaces. The input acquisition of this system consists of three modules, each of which has 32 data channels (plus two clock channels), using exactly the same functional structure. The third module has additional functions such as clock input and output, and control. The main reasons for adopting this structure are, first, to avoid the main acquisition board being too large and the components being too dense, which will cause difficulties in heat dissipation (due to the large number of high-speed devices), and second, the system structure is flexible, and 32, 64, and 96-channel configurations can be selected as needed.

　　The control and management, data processing and data display of the logic analyzer are completed by the embedded computer. Therefore, the design of the system hardware mainly focuses on high-speed data capture and the interface with the microcomputer, while the software design mainly focuses on system management, data post-processing and data display.

　　Figure 1 400MHz/102-channel virtual logic analyzer block diagram

　　3 System Hardware Design

　　High-speed data capture in the 400MHz/102-channel virtual logic analyzer is achieved by the control circuit completing trigger control and data access control, and the control circuit also realizes the interface with the microcomputer.

　　3.1 Data Storage Principle

　　When performing state analysis, the logic analyzer works synchronously with the system under test. In order to make the state data stored in the memory consistent with the data flow of the system under test, the following conditions should be met:

　　DATA*/FWEN=f(sclk,trw,dtc)*data　　　　　　(1)

　　In formula (1), DATA is the data stored in the logic analyzer; /FWEN is the write enable control of the main memory FIFO of the logic analyzer; sclk is the state (external) clock; trw is the trigger word; dtc is the data control; data is the data of the system under test. From formula (1), we can get the following formula:

　　DATA=data　　　　　　　　　　　　　　　　　(2)

　　The condition for this is that the /FWEN signal must have a strict relationship with the sclk, trw, and dtc signals. According to the controllability theory in the testability design of digital systems, the CAMFLOT[2] method (Computer Aided Measure For Logic Testability) is applied, and we have:

　　In formulas (3) and (4), CY is the controllability, and its value is ε(0,1); CTF is the controllable transfer factor; N(0) and N(1) are the total number of times "0" and "1" appear at the circuit output when all different input values ​​are added to the circuit input. From formula (3), we know that when the control signals such as sclk, trw, and dtc are reliably set, we can calculate:

　　CY(/FWEN)=1 (5)

　　That is, /FWEN is fully controllable to ensure that DATA=data.

　　When performing timing analysis, the logic analyzer and the system under test work asynchronously. At this time, the following conditions must be met:

　　DATA*/FWEN=f(trw)*data (6)

　　At the same time, taking the sampling frequency as 5 to 10 times the operating frequency of the system under test can effectively store the data stream required for observation, and obtain a sufficient observation range and satisfactory time resolution. [page]

　　3.2 Trigger control implementation principle

　　According to the data storage principle, one of the keys to correctly store the logic analyzer FIFO data is the control of trw, that is, to realize the trigger control such as start, end, delay (clock, event), random, sequence, combination and limitation through trigger recognition. Using the bit storage mapping method, high-speed EPLD[3] is combined with the trigger memory, and the principle block diagram of trigger control is designed as shown in Figure 2.

　　In Figure 2, D0~Dmk-1 are the measured data. The trigger RAM data bit width is n, the address width is k, and the number is m, so the width of the observable data stream is m·k. When k≥n, the maximum sequence trigger or combination trigger recognition level L is:
L≦2n-1 (7)

　　Figure 2 Trigger control implementation principle block diagram

　　4 System Software Design

　　Using the graphical interface operating system Windows and the Windows-based visual programming platform C++Builder, the software consists of 15 windows and 5 unit files. The relationship between the main windows is shown in Figure 3.

　　Figure 3 System software windows and their relationships

　　5 Conclusion

　　The logic analyzer has a complex structure and high technical requirements. The design ideas and methods based on the concept of virtual instruments described in this article greatly simplify the hardware circuit due to the softening of some hardware functions. At the same time, EPLD devices are used to reduce the instrument cost, improve the reliability and performance of the instrument, and the function is easy to expand. The 400MHz/102-channel logic analyzer passed the technical appraisal hosted by the Military Industry Pre-Research Bureau of the Ministry of Information Industry on December 28, 2000.