Oscilloscope Advanced Trigger Types and Controls (Part 1)

As waveforms, especially digital signals in parallel and serial buses, become more and more complex, the old edge trigger has too many limitations to be used as the only acquisition method. As the analogy mentioned above, edge triggering cannot provide enough information for the oscilloscope to tell the driver "where to stop" to take the best photo.

 

Advanced triggering responds to more strictly specified conditions on incoming signals, such as making it easy to detect pulses that are narrower than they should be. This condition would be impossible to detect using only edge triggering. Advanced trigger control features can isolate specific events of interest.

 

The Pinpoint trigger system allows a high degree of optional control over the events you are trying to capture. You can trigger on pulses defined by amplitude (such as runt pulses or pulses); trigger on pulses defined by time (pulse width, glitch, slew rate, setup and hold time, and timeout); trigger on amplitude and time using window triggering; or characterize by logic state or pattern (logic triggering). The intuitive user interface allows for quick setup of trigger parameters, allowing for extensive flexibility in test setup and maximizing productivity. The advanced trigger menu is displayed by selecting the trigger setup menu item using the mouse or the oscilloscope touch screen, or by pressing the ADVANCED button in the TRIGGER section of the front panel.

 

Many oscilloscopes offer dual triggering. The A (main) trigger is usually a full-featured system that includes advanced triggering; the auxiliary B trigger is limited to edge pattern detection. The A trigger acts as a qualifier, and when the A trigger occurs, the B trigger can look for a specified voltage threshold.

 

Tektronix's DPO7000 and MSO/DPO/DSA70000 series oscilloscopes with Pinpoint trigger technology are different. They have two complementary trigger circuits that allow comprehensive advanced trigger qualification on A events and B events, which is called A and B event dual triggering. Pinpoint triggering provides A and B event dual triggering for the following trigger types: edge, glitch, width, runt pulse, timeout, transition time, setup and hold time, pattern, state and window.

 

Glitch trigger

Glitch triggering only accepts (or rejects) events with pulse widths below a specified limit. Negative, positive, or either polarity can be selected. This trigger control capability allows examination of the cause of a glitch (no matter how rare) and its effect on other signals. The Pinpoint Trigger System user interface allows searching for glitches as small as <300 ps, ​​detection of glitches as wide as 150 ps, ​​and a minimum re-arm*1 time of 300 ps. In Figure 1a, glitch triggering is used to track down a crosstalk problem. Channel 1 triggers on the glitch that causes logic uncertainty in the system, while Channel 4 identifies the signal causing the glitch on an adjacent data line.

Figure 1a. Glitch triggering.            

Width Trigger

Width triggering allows accepting (or rejecting) triggers defined by only pulse widths that are between two specified time limits, useful for observing intersymbol interference (ISI). ISI occurs when a bit state changes after a long sequence of bits with the opposite state, such as when a "1" occurs after a sequence of "0s". In 8B/10B encoding, the bit time may vary from 1 to 5 bits, while the width of PRBS signals varies much more. In width triggering, positive or negative pulse polarity can be selected. Pulse widths can range from 150 ps to 1 s, with user interface controls supporting resolutions up to 300 ps and a 300 ps rearm time. In Figure 1b, width triggering is used to trigger only on positive pulses that are 4 bits long in a fast serial bit stream.

 

Figure 1b. Width trigger    

Runt Pulse Trigger

Runt pulses in digital signals often represent metastable conditions that can put digital systems into an unknown state. Runt triggering allows triggering to be specified by accepting only pulses that enter and exit between two specified amplitude thresholds. Time-qualified runt pulses can be used with a minimum pulse width of 200 ps and a re-arm time of 300 ps. Positive, negative, or either short pulse polarity can be selected. In Figure 1c, the runt trigger level is set to the lowest threshold of the logic family, and the oscilloscope will capture pulses below this indicator. [page]

Figure 1c. Triggering on a runt pulse.

Timeout trigger

Sometimes clock or data signaling “dead time” is designed into a system. However, dead time can cause system communication errors if the correct timing relationship with other system times is not established. It is usually best to trigger on these dead times, find them, and then investigate their timing with other signals. By using a timeout trigger, you can trigger on an event that remains high, low, or either state for a specified period of time, which can be adjusted from 300 ps to 1 s using the time control function. In Figure 1d, a timeout trigger determines dead time in a bidirectional bus data stream. The timer is set to 100 ns, which is guaranteed to be greater than any data width in the signal. The dead time is given as 340 ns. The acquisition counter finds 45 timeout events in 10 seconds, indicating that this event occurs only .0000015% of the time in the repetitive bit stream.

Figure 1d. Timeout trigger.

Transition time trigger

If an edge (transition time) is faster than necessary for the operating environment, it may emit objectionable energy. If the transition time is too slow (such as on a clock), it may cause circuit instability. Transition time triggering allows the system to trigger when the time interval from a low-to-high threshold and/or from a high-to-low threshold is slower (greater) or faster (shorter) than a specified time, where positive, negative, or either polarity can be selected. In Figure 1e, the transition time trigger is used to identify clock edges slower than 3.5 ns.

 

Figure 1e. Transition time triggering.

Setup and Hold Trigger

Setup and hold violations can cause data errors that can cause the entire system to oscillate. Setup and hold triggering makes it easy to capture specific signal quality and timing details when synchronous data signals fail to meet setup and hold specifications. If a positive or negative data edge (transition) occurs within the setup and hold window specified by the positive (or negative) clock edge, an acquisition can be triggered. Only setup and hold triggering allows deterministic capture of individual setup and hold violations that would otherwise be missed. Figure 1f shows 1165 acquisitions captured with setup and hold violations of less than 300 ps.

 

Figure 1f. Setup and hold triggering. [page]

Window Trigger

In many high-speed designs, multiple internal component buses share the same bus on a single board. Hardware or software controlled buffer arrays are used to multiplex the correct data onto the main bus. The multiplexer logic is designed to allow only one unit to use the bus at any one time. Design errors can result in bus contention, where a bus with two logic levels experiences an "intermediate" state where the signal is neither a '1' nor a '0'. Window triggering makes it easy to capture bus contention. With the window trigger feature, the oscilloscope triggers on events that enter (or exit) a window defined by two user-adjustable thresholds. In addition, the time qualification indicator on the window trigger can be used to form a rectangular time window that triggers the acquisition if the signal enters or exits this window. The minimum window width is 150 ps, ​​and the minimum re-arm time is 500 ps. Figure 1g illustrates a captured bus contention event. The trigger levels are set to the high and low threshold voltages of the appropriate logic family.

 

Figure 1g. Window triggering.

Logical Limitation

The Pinpoint trigger system also provides the option to logically qualify all of the advanced trigger types above (Glitch, Width, Runt, Timeout, Transition Time, Setup and Hold, Window), providing another powerful tool for isolating events. Figure 2 illustrates the use of logic qualification to capture setup and hold times, where Channel 1 (yellow) and Channel 2 (blue) are clock and data, respectively. The trigger events for Channel 3 (magenta) and Channel 4 (green) are both qualified to logic high. Only when the logic condition is met,

The acquisition will be triggered only when the setup and hold time are violated. In digital circuits, it is usually necessary to define the trigger condition based on the logic state of the observed signal. A 4-channel oscilloscope can use the logic state of up to four inputs to trigger the oscilloscope.

Figure 2. Logic-qualified setup and hold triggers.

There are two types of logic triggers in the Pinpoint trigger system:

◆Logical pattern trigger

◆Logical state trigger

◆Logical pattern trigger

 

Logic triggering (Figure 3a) allows triggering an acquisition on any logical combination of the input channels provided, which is particularly useful for verifying digital logic operations. When the input channels meet the logic pattern (AND, OR, NAND, NOR), the oscilloscope triggers.

The traditional logic families (TTL and ECL) provide predefined threshold levels, and the thresholds can also be set using USER for logic families, such as high-speed CMOS. On the MSO70000 series, logic patterns up to 20 bits wide can be defined as trigger conditions. This is particularly useful for isolating specific system states in complex designs, such as memory buses where timing verification is critical.

 

Figure 3a. Logic pattern triggering.

Logic state trigger

Similar to logic pattern triggering, in logic state triggering, the trigger is defined by any logic pattern of channels 1, 2, and 3 (and channels D0-D15 on the MSO70000) clocked by an edge on channel 4 (and Clk/Qual on the MSO70000), as shown in Figure 3b. The system can be triggered on either the rising or falling edge of the clock. This type of trigger is useful when debugging propagation delay and metastability issues in circuits that contain triggers and shift registers. Logic state triggering can be used to debug parallel buses with discrete clock lines and multiple data signals; serial triggering (discussed later) is useful for triggering on embedded clock data in serial buses.

 

Figure 3b. Logic state triggering.