Oscilloscope as "Engineer's Eyes" Application Case

In July 2014, we launched a high-end power quality equipment development project. The technical requirements of this project are many sampling points, high data rate, complex algorithms, large data storage, multiple network interfaces, and multiple advanced applications. Faced with such a situation, we decided to build a new hardware platform to meet the product requirements through a lot of analysis and evaluation. After analyzing and comparing multiple processors, a brand-new hardware architecture was finally produced: dual-core CPU with FPGA, Switch, DOM disk, etc. to realize data acquisition, transmission, calculation, storage, communication and other functions. After some efforts, our board was quickly proofed and returned to the board, and SMT was completed, officially entering the software and hardware debugging stage. After completing the test of the main components of the small system (CPU, DDR, Flash, etc.), we entered the development phase of the peripheral components of the small system. When doing the SATA-DOM disk test, we found that the DOM disk could not be connected. With the cooperation of the software engineer, it was quickly located that the differential LVDS reference clock output by the differential crystal oscillator to the CPU failed to lock stably, causing the controller to fail to work properly. When searching for oscilloscopes for testing high-speed signals within the company, we found that most of them had very low bandwidth and were not equipped with active differential probes. We could not see the waveform at all, and thus could not determine whether it was a problem with the principle design, PCB, device soldering, or other issues. The project was stuck. The next step was to search everywhere for an oscilloscope that could be used. I was so sweaty!

It was a coincidence. Our company had been preparing to configure a high-end oscilloscope. Due to the long procurement process, we had been in contact and product evaluation with Tek, R&S, and Agilent. Through our procurement, we quickly contacted the sales of these three companies. R&S was the first manufacturer to send us a test oscilloscope prototype at the fastest speed after contacting us. It was like sending carbon in the snow, and a long drought was met with a sweet rain! On the day I got the oscilloscope test prototype, I quickly unpacked it, powered it on, and prepared for signal testing. Because I had been using oscilloscopes from the other two companies before, I was not very familiar with the software interface and operation buttons of the R&S oscilloscope at the beginning, and the operation was relatively awkward. After a simple exploration, I was able to do simple tests, but I couldn't quickly get high-speed signal measurements done, so I had to ask for help from technical support. Through procurement, I successfully contacted the sales engineer-Yang Yu, and with his help, I quickly contacted the technical support engineer-Li Xing. With the remote assistance of Mr. Li, I was able to quickly perform high-speed signal measurements and capture the clock waveform. Engineer Li was worried that I might not be able to handle it well, so he came to our company the next morning to provide on-site training and guidance. Based on the captured clock waveform, we conducted a comprehensive analysis. Engineer Li's profound technical knowledge provided important ideas for my analysis of this strange problem.

First, the principle analysis, the preliminary conclusion is: there are not too many problems in the hardware principle design. This is an LVDS clock crystal that sends out a differential LVDS clock and is connected to the CPU side through AC coupling (Figure).

Since we couldn't find the problem in principle, we could only focus on measuring the waveform and analyzing it in detail. We used an R&S oscilloscope to capture the clock output waveform on the CPU side using an active differential probe (Figure 1) and an active single-ended probe (Figure 2).

Figure 2 Single-ended probe measurement

From the figure, we can see that the clock quality is poor on the CPU side, the signal differential swing is insufficient, the common mode voltage is out of range, and the waveform is severely distorted. It is natural that the PLL on the CPU side cannot lock this input clock signal. Is there a problem with the PCB design? The screenshot of the PCB routing is as follows:
 

Then, for the crystal oscillator, the bare chip power supply is measured according to the test method described in the manufacturer's information provided by the device. The drawing is as follows: (Figure 3)

Figure 3 Recommended test circuit

 

Connect the crystal oscillator to 3.3V power directly, disconnect the existing load, connect a 100 ohm resistor between the differential PN signals, and measure the signal. It is found that there is indeed a problem with the crystal oscillator output. The output swing of the differential signal and the single-ended signal is small, and the signal distortion is serious (similar to Figure 1 and Figure 2). From this, it can be basically concluded that the crystal oscillator was purchased through informal channels, and its quality is so poor! Based on the above test results, two problems are summarized here, and verification solutions are formulated respectively:

• Purchase a differential crystal oscillator through formal channels and prepare for testing;
• Analyze why the signal quality can be improved when the ground wire of the R&S oscilloscope passive probe is connected to the negative end of the differential signal;

For solution 2, I simulated the resistance and capacitance distribution parameters marked on the probe and conducted some tests: for example, the negative end flying line, connecting to the ground through series resistance, capacitance, etc., all failed to match the probe bottom line contact phenomenon. After careful analysis, I found that the output voltage ground wire of my single-board DC regulated power supply was not grounded with the mains power line (Figure 4), that is, the dotted line in the figure was not connected. At this time, I used a multimeter to test the ground wire of the oscilloscope probe and the GND output of the DC source (-end), and found that there was a very small voltage difference.

Figure 4 Test network diagram

After the Earth common ground is completed (connect the dotted line), the network test is performed using Figure 5 below. At this time, the PLL still cannot lock. When the ground wire of the oscilloscope probe is connected to the negative pole of the differential signal, the PLL cannot lock either.

Figure 5: Construction site test network diagram

It can be seen that this problem has nothing to do with the oscilloscope and the probe itself. Through analysis, it was found that because the probe ground is connected to the quasi-earth of the power line, it is floating with the output ground of the voltage regulator, and there is a voltage difference. At this time, it is concluded that when the negative end of the current bad crystal oscillator is connected to a DC voltage of a certain amplitude, it is equivalent to increasing the common mode voltage of the differential crystal oscillator input, which improves the quality of the LVDS signal to a certain extent. Therefore, another experiment was conducted. By connecting the negative end of the differential crystal oscillator to a 1.2V voltage (Figure 6), a 1.2V common mode voltage was artificially provided. At this time, it was found that the PLL was locked successfully and the DOM disk worked normally.

Figure 6 Differential signal negative pole flying wire test diagram [page]

At this time, the waveforms measured by active differential and active single-ended probes are:

Figure 7 Measured by active differential probe
    
 

Figure 8 Active single-ended measurement

From the above two figures, we can see that although the PLL is locked, it can be seen that the P and N signals are not 180 degrees crossed, and the common mode voltage is not correct. However, the differential signal swing is large enough (see Figure 7) to enable the LVDS PLL to work.

For the first solution, we purchased a differential crystal oscillator from a Taiwanese company. After welding, SATA-DOM can work stably directly, which further verifies that the differential crystal oscillator used initially has quality problems. Of course, we also conducted detailed waveform tests on the new differential crystal oscillator (Figure 9 and Figure 10), and found that the indicators are consistent with the device data and meet the LVDS signal standard. We also conducted a read and write file stress test on the DOM disk, and it has been working normally so far, and this problem has been successfully solved.

Figure 9 Measured by active differential probe

Figure 10 Active single-ended measurement

In the whole process of problem location and solution, the R&S oscilloscope really played the role of "engineer's eyes", accurately measuring the high-speed measured signal and obtaining the desired waveform, which provided us with strong evidence for problem analysis. The convenient and fast window interface touch operation greatly improved the measurement speed. At the same time, thanks to Yang Yu and Li Xing for their strong support.