Surge testing of solid-state USB switches and other overcurrent protection devices

　　Overview

　　With a 1.2A current limit, it is often assumed that the circuit protection IC will remain in full control during a fault or short circuit. In reality, there is often a delay after the current limit condition is reached before the switch is actually turned off. In a hardware short, the current rises rapidly, first reaching the DC limit condition and beginning to turn off the switch (DC limit can be very accurate, but reacts slowly, which prevents surges and other false fault events from causing the switch to close). Although the switch opens in a short time, the peak current may already be well above the DC threshold. When the lead parasitic inductance is lower, the current may rise faster. See Figure 1.

　　Current limiting via resistors

　　We use the MAX1558 USB switch with low lead inductance. When a hardware short circuit occurs, the current is limited by the chip's internal protection switch. When the protection circuit finally disconnects the switch, the peak current (I) can be measured, as shown in Figure 2. The peak current flows through the parasitic inductance (LSTRAY) at the input, and the following energy (E) will be stored:

　　E = 2 × LSTRAY × I2

　　Where does the energy go when the circuit breaker or protective switch is disconnected?

　　Figure 1. This circuit shows the current path in a hardware short and the current path driven by parasitic inductance.

　　Figure 2. The waveform shows the short-circuit response with a 10µF CBYPASS. From the VIN waveform, we can see that the input voltage surges to 8.6V due to the current change.

　　As can be seen from Figure 2, the input current (IIN) quickly rises to 48.8A and then is limited. When the switch is turned off, the current drop rate can be measured. When IIN drops at 20A/μs, VIN will surge to 8.6V (VMAX). The circuit inductance can be calculated according to the following formula:

　　(VMAX - VIN) = di/dt × LSTRAY

　　When VMAX - VIN = 3.6V, di/dt = 20A/μs, LSTRAY = 180nH. [page]

　　Therefore, according to E = 2× LSTRAY × I2, 214µJ of energy is stored in LSTRAY when the fault ends. A bypass capacitor is needed to absorb this energy and limit the voltage rise. If a 10µF input capacitor is selected and the initial voltage is 5V, the initial energy storage is:

　　V2 × C × V2 = E

　　Now, assuming that all the energy stored in LSTRAY is eventually transferred to the input capacitor CBYPASS, then:

　　Initial energy + parasitic energy = final energy

　　125μJ + 214μJ = 339μJ

　　339μJ is the final energy in the input capacitor, according to:

　　V2 × C × V2 = E

　　or:

　　V2 × 10μF × V2 = 339?J

　　Solving for V, we obtain: V = 8.23 ​​V. This is very close to the measured value of 8.6 V in Figure 2.

　　If the input bypass capacitor is only 0.1μF, the input voltage will rise to a destructive voltage. Recalculating based on 0.1μF:

　　Initial energy + parasitic energy = final energy

　　1.25μJ + 214μJ = 215μJ

　　and:

　　V2 × 0.1μF × V2 = 215?J

　　Solving for V, we get: V = 65.6V!

　　Obviously, this process will damage a device rated for only 5.5V. The waveform for this hardware short is shown in Figure 3. Note that the output also shoots up to 9.8V. This is because the switch is disconnected after the short. It is also due to the fast di/dt change during this test. Usually the di/dt is determined by the turn-off characteristics of the power device. For the USB port, the circuit is up to the end user - any possibility exists, but it is within control. The cause of such an extreme fast turn-off may be a broken cable, a problem with the connector, or a mechanical failure during the connection process, as shown in this example.

　　Figure 3. As can be seen from the waveform, if the input capacitor is only 0.1?F, the input voltage will surge to a potentially damaging high voltage.

　　Of course, the voltage will not surge to the theoretical value of 66V. This is because the chip has an integrated Zener protection tube that can clamp the voltage rise and may be damaged due to energy absorption. During the overvoltage process, the extra energy is absorbed by the silicon chip. The following Figure 4 is a time expansion diagram of Figure 3.

　　Figure 4. Time expansion of Figure 3. Note the high di/dt rate during the switch off time. Some of the stored energy has already been delivered to the output! This will damage the USB switch.

　　As can be seen from Figure 4, for the same circuit, a larger input bypass capacitor can better handle the parasitic energy caused by a hardware short circuit, thus providing additional protection. Typically, a printed circuit board (PCB) with a ground plane has less parasitic inductance than the leads under test or other connections in the lab. When testing in the lab, it is very difficult to reduce the parasitic inductance of the connecting wires and test equipment. [page]

　　Input inductance limits peak current

　　Figure 5 shows that even with input lead inductance as high as 1.3µH, the device can still survive if a 10µF bypass capacitor is used.

　　Figure 5. This waveform shows the case when the parasitic inductance caused by long input leads is large (1.3?H), and the same 10?F input bypass capacitor is used. Note that the input current rises and falls slowly. When the input voltage exceeds 8V, the device will also experience Zener breakdown, and current will be leaked to the output (as shown by IOUT in the waveform), but the switch will not be damaged.

　　As can be seen in Figure 5, the larger inductance slows down the rate at which the input current rises and falls. This is important because the rate of change of current is greatly reduced when the inductance is larger. Because the energy stored in the inductor is proportional to the square of the current and proportional to the inductance, a higher peak current will store more energy. The energy stored in a 1.3μH inductor is only 419?J:

　　125μJ + 419μJ = 544?J

　　and

　　V2 × 10μF × V2= 544μJ

　　Solving the above equation for V, we obtain: V = 10.43V.

　　Although the device survives this hardware short, it is recommended to use a larger input bypass capacitor to limit the maximum voltage to below the limiting parameters specified in the data sheet.

　　in conclusion

　　If the energy stored in parasitic inductance is not considered in the design, USB devices may be damaged due to overvoltage. As shown in Figure 5, the input inductance can be the limiting factor of the peak current, and from Figure 2, it can be seen that the resistor can also limit the current. If the current is limited below the level that causes device damage, lower inductance can help improve the safe operation of the circuit. If the current is not properly limited, the energy released in the low inductance situation can quickly reach destructive levels. Special care is needed to avoid this situation. In the circuit shown in Figure 2, the current is limited by a 0.1Ω resistor. Although reducing the inductance will increase the speed of current rise, if appropriate current limiting measures are taken, smaller inductance can help reduce the energy storage.

　　Most PCB designs have a ground plane underneath the protection switch and input and output paths, and the inductance is usually much lower than 180nH. For a 1/16-inch wide PCB trace with a ground plane underneath, approximately 10nH inductance will be generated per inch of length. The required input bypass capacitor should be determined based on the specific application environment. From the measurement and analysis results of the inductance, a larger bypass capacitor may be required to ensure the reliability of the system. Of course, it may also be possible to allow the input bypass capacitor to be reduced.