A frequency multiplication method to improve DDS performance

In the past two decades, with the development of digital integrated circuits and microelectronics technology, a new frequency synthesis technology has emerged - Direct Digital Synthesize (DDS). The emergence of DDS has led to the second revolution in the field of frequency synthesis. DDS has the advantages of relatively wide bandwidth, fast frequency agility, high frequency resolution, continuous output phase, broadband orthogonal signal output, programmable, fully digital and easy integration. However, its all-digital structure has caused the main disadvantages of DDS: First, according to the sampling quantity, the highest frequency of the output signal will be lower than half of the reference clock, so if the output frequency is to be increased, it will be limited by the speed of the device (such as DAC, ROM); second, the DDS output signal has large spurious parasitic components, especially the high frequency output, which cannot achieve the spectrum purity of PLL frequency synthesis; third, the power consumption of DDS is proportional to its clock frequency, so in places where power supply is limited and a higher frequency output is required, DDS has limitations. How to overcome the main shortcomings that limit the widespread application of DDS is the main topic of DDS technology research in the world. This paper will use the frequency multiplication method to expand the upper frequency limit of DDS and improve the DDS spurious level.

1 Basic Principles of DDS and Its Spurious Levels

The theoretical basis of DDS is the Nyquist sampling theorem. According to this theorem, for a periodic sinusoidal continuous signal, the phase/amplitude can be sampled along its phase axis at equal phase intervals to obtain a discrete phase amplitude sequence of a periodic sinusoidal signal, and the analog amplitude is quantized, and the quantized amplitude is encoded with corresponding binary data. In this way, a periodic sinusoidal continuous signal is converted into a series of discrete binary digital quantities, which are then solidified in a read-only memory ROM by certain means. The address of each storage unit is the phase sampling address, and the content of the storage unit is the quantized sinusoidal amplitude. Such a read-only memory constitutes a sine function table corresponding to the phase sampling within a 2π period. Because it stores the amplitude of a periodic sinusoidal waveform, it is also called a sinusoidal waveform memory. For a continuous sinusoidal signal, its angular frequency ω can be expressed by the phase slope Δφ/Δr. When the angular frequency ω is a certain value, its phase slope Δφ/Δt is also a certain value. At this time, the phase of the sine wave signal is linearly related to time, that is, φ=ω×Δt. According to this basic relationship, under the action of a clock signal of a certain frequency, the obtained sine wave waveform memory is scanned by a sampling address generated by a linear counting timing generator, and then the data in the waveform memory is periodically read. Its output can be synthesized into a complete sine wave signal with a certain frequency through a digital-to-analog converter and a low-pass filter.

The basic principle block diagram of DDS is shown in Figure 1. It is mainly composed of a standard reference frequency source, a phase accumulator, a waveform memory, a digital-to-analog converter, and a low-pass smoothing filter. Under the control of the clock pulse, the frequency control word K is obtained by the accumulator to obtain the corresponding phase code, and the phase code addresses the waveform memory to perform phase code-amplitude code conversion to output different amplitude codes, and then passes through the digital-to-analog converter to obtain the corresponding step wave, and finally the step wave is smoothed by the low-pass filter, that is, the continuously changing output waveform determined by the frequency control word K is obtained. Among them, the reference frequency source is generally a highly stable crystal oscillator, and its output signal is used for the synchronous operation of various components in the DDS. Therefore, the frequency stability of the synthetic signal output by the DDS is the same as that of the crystal oscillator. The phase accumulator is the core of the DDS, as shown in Figure 2. It consists of an N-bit binary adder with a word length of N and an N-bit phase register sampled by a fixed clock pulse. The output of the phase register is internally connected to one input end of the adder, and the other input end of the adder is the frequency control word K input externally. In this way, when each clock pulse arrives, the phase register samples the word K. In this way, when each clock pulse arrives, the phase register samples the sum of the value of the phase register in the previous clock cycle and the frequency control word K, and uses it as the output of the phase accumulator in this clock cycle.

When the frequency synthesizer is working normally, under the control of the standard frequency reference source (the frequency control word K determines the corresponding phase increment), the phase accumulator continuously accumulates the phase increment linearly. When the phase accumulator is full, an overflow will occur, thus completing a periodic action. This action cycle is a frequency cycle of the DDS synthesized signal. Therefore, the frequency and frequency resolution of the output signal waveform can be expressed as follows:

fout=Kfc/2 N (1)

fmin=fc/2 N    (2)

Where: fout is the output signal frequency; fmin is the output signal resolution; K is the frequency control word; N is the phase accumulator word length; fc is the operating frequency of the standard reference frequency source.

From equations (1) and (2), it can be seen that the frequency of the DDS output signal mainly depends on the frequency control word K, and the phase accumulator word length N determines the frequency resolution of the DDS. When K increases, fout can be continuously increased. According to the sampling theorem, the maximum output frequency must not be greater than fc/2, but when the working output frequency reaches about 40% fc, the phase jitter of the output waveform is very large. According to experimental results, it is more appropriate to have an output frequency less than fc/3 in actual operation. At the same time, when N increases, the resolution of the DDS output frequency becomes finer.

Theoretically, the phase noise of the DDS output signal can improve the phase noise of the reference clock signal by 20lg(fc/fout)dB. However, the digital processing of DDS also brings disadvantages. Rich spurious signals are output along with the main frequency, making the reduction of spurious signals a major problem. Figure 3 shows the sources of spurious signals of DDS, which mainly include the following three factors:

(1) ξDA (n) is the error introduced by the D/A converter, which is caused by the non-ideal characteristics of the D/A converter. The non-ideal characteristics of the DAC include: differential and integral nonlinearity, peak current during the D/A conversion process, and conversion rate limitation.

(2) ξT(n) is the error caused by the limited word length of the ROM storage data. Since the number of bits stored in the ROM is limited to D, the amplitude quantization process will produce a quantization error ξT(n);

(3) ξP(n) is the error caused by phase truncation. In DDS, the number of bits L of the phase accumulator is generally much larger than the number of bits W of the ROM addressing. Therefore, when the output of the accumulator addresses the ROM, its LW low bits must be discarded, which inevitably produces a phase error, called the phase truncation error ξP(n). This error is the main cause of DDS output spurious.

2 Methods to extend the upper frequency limit of DDS

According to the previous analysis, the low output frequency and high spurious level of DDS limit its application in broadband, high stability, and high purity spectrum radar signals. In order to reduce spurious signals, the advantage of DDS's relatively wide bandwidth cannot be fully utilized. We can only select a limited bandwidth with low spurious signals in DDS and expand its upper frequency limit by frequency doubling. This is the reason why DDS frequency doubling is used to obtain broadband signal waveforms.

There are many ways to expand bandwidth, including direct frequency multiplication using a frequency multiplier, frequency multiplication using a multiplier, separation of the upper and lower sidebands using an image rejection mixer, synthesis using DDS quadrature outputs, combination of DDS and mixers, combination of DDS and phase-locked loops, and multi-channel parallel DDS. This article uses the direct DDS frequency multiplication method, which is described in detail below.

Figure 4 is a block diagram of the principle of direct frequency doubling of DDS. The smaller signal of 0 to 20 MHz outputted by the Stel-1175 DDS is pre-amplified, passed through the narrow-band filter at the back, and added to the first-stage transistor frequency multiplier through the coupling capacitor. The DC operating point of the transistor is adjusted to make it work in the Class C working state. Due to the nonlinear characteristics of the transistor, multiple harmonics are generated at its signal output end, and then the double frequency signal of the input signal is effectively extracted through the bandpass filter. After four times of double frequency, the output frequency is 198 to 220 MHz. Since the bandpass filter has a large attenuation (insertion loss -10 dB), the output signal is very small, so a transistor linear amplifier is added at the end to obtain the signal of the required amplitude.

Compared with many frequency multiplication methods, transistor frequency multiplication has the advantages of simple circuit, large branch state range, high gain, and low stray harmonic level. Therefore, the transistor frequency multiplication scheme is adopted in the DDS frequency multiplication circuit. The basic principle is to use the transistor in the Class C working state to cause the distortion of the input signal waveform, thereby generating its harmonic components, and then extract the required harmonic components through the post-stage frequency selection circuit. In the transistor frequency multiplication circuit of the DDS frequency multiplication module, 2SC3358 is selected as the transistor for frequency multiplication. It is a transistor with low phase noise, high reliability, high stability, and a large dynamic range. The working principle of transistor frequency multiplication will be briefly analyzed below.

The relationship between the voltage and current of each level in the double frequency circuit is shown in Figure 5. Due to the nonlinearity of the transistor, the fundamental harmonics are generated at the collector, making the output circuit resonate with the second harmonic, so the frequency of Vc is twice the fundamental signal frequency. At the same time, Vcmin and Vbmax still meet at the same point. The expressions of the instantaneous collector voltage and the instantaneous base voltage can be written as:

vc=Vcc-Vcmcos2ωt     (3)

vB=-VBB+Vbmcosωt (4)

For comparison, the curve of bc=Vcc-Vcmcosωt when used as an amplifier is also drawn with a dotted line in Figure 5. It can be seen that during the time when ic is flowing, the collector instantaneous voltage of the frequency doubler rises faster. Therefore, under the same Vcmin value, the collector power loss Pc of the frequency doubler is much greater than when it works normally at the fundamental frequency, that is, the collector efficiency ηc is much lower. In order to avoid Pc being too large, the collector current angle θc of the frequency doubler should be reduced to reduce Pc and increase ηc.

Since Vcmin is the same, the voltage utilization coefficient ξ=Vcmn/Vcc of the two is also the same. Now, starting from the same iCmax and rCmin conditions, we compare the output power and efficiency of the doubler and amplifier:

Pon=1/2VcmIcmn=1/2(ξVcc)iCmaxan(θc)     (5)

ηc=(Pon)/(Po)=[(1/2)VcmIcmn]/(VccIco)=(1/2)ξgn(θc)     (6)

式中：gn=(Icmn)/(Ico)=[an(θc)]/[a0(θc)]

From formula (5), it can be seen that the output power of the nth harmonic frequency multiplier is proportional to the decomposition coefficient an(θc) of the nth harmonic. From Figure 5, it can be seen that:

θc=120° a1(θc)=0.536(max) θc=60° a2(θc)=0.276(max) （7）

Therefore, in order to maximize the output power of the frequency multiplier, when n=2, θc should be around 60°. Compared with the amplifier output power when θc=120°, the following is true:

(Po2)/(Po1)=[a2(60)°]/[a1(120°)]=0.52≈1/2 (8)

It can be seen that when the optimal pass angle is used, the output power of the quadratic frequency multiplier can only be approximately equal to 1/2 of that when it is used as an amplifier. At the same time, from formula (8), it can be found that its efficiency also decreases with the increase of the frequency multiplication number n.

From the above discussion, we can know that as the frequency multiplication number n increases, its output power and efficiency decrease. At the same time, the higher the n value, the smaller the optimal θc value. In order to reduce θc, it is necessary to increase the base reverse bias -VBB of the frequency multiplier. After VBB increases, the base excitation voltage Vbm must also be increased. For transistor circuits, increasing the excitation voltage and bias may cause the reverse bias of the emitter junction to exceed the breakdown voltage V(BR)EBO. Based on the above reasons, the frequency multiplication number n of this frequency multiplier usually cannot exceed 3 to 4. Therefore, in the DDS frequency multiplication module, the frequency multiplication number is selected as 2.

On the basis of completing the design of the scheme and system block diagram, the design of the entire DDS frequency multiplication module scheme and PCB diagram was further completed. After completing the board making and system assembly, the system was debugged and the final test results were obtained. The test results are as follows:

Input frequency range: 12.375～13.75MHz

Input power range: -25～0dBm

Output frequency range: 198～220MHz

Output power range: +8.0～+11.0dBm/when input power is -9dBm

Spurious level: ≤-60dBc

Harmonic level: ≤-35dBc

Phase noise: ε (1kHz) ≤-90dBc/Hz; ε (10kHz) ≤-100dBc/Hz

Figures 6 and 7 show the frequency spectra of several frequency points measured by ADVANTEST R3465 spectrum analyzer.

According to the above analysis, when the DDS output signal frequency of Stel-1175 is 0～20MHz and the power is -25～0dBm, the DDS upper limit frequency extended by the DDS frequency multiplication module is 198～220MHz, the output power is +8.0～+11.0dBm (when the typical input power is -9dBm), the spurious level is less than ≤-60dBc, and the harmonic level is less than ≤-35dBc. From the above indicators, it can be known that the DDS frequency multiplication module can meet the engineering application requirements in the fields of communication, radar, electronic countermeasures, navigation, telemetry and remote control, and electronic instruments.

In the field of electronic countermeasures, the DDS frequency multiplication module can be used as the transmitter excitation source and the ideal local oscillator source of the receiver in the frequency hopping secure communication system and the radar system with high stability and high purity spectrum. This can increase the frequency hopping speed and widen the frequency hopping range to improve the anti-interference ability of the frequency hopping communication system and the radar system.