Building a Digitally Programmable Gain Amplifier with Negative Time Constant

A digitally programmable gain amplifier (DPGA) amplifies or attenuates an analog signal to maximize the dynamic range of an analog-to-digital converter (ADC). Most monolithic DPGAs use a multiplexed multiplying digital-to-analog converter (DAC) in the feedback loop of an op amp, such as the Maxim LTC6910 and National Semiconductor LPM8100, so that the input code to the DAC sets the closed-loop gain of the amplifier. Instead of using a monolithic DPGA, a negative time constant-based DPGA is constructed using two op amps and three analog switches.

Engineers are no doubt familiar with the e–t/RC convergence exponent, where the capacitor within an RC circuit discharges to zero in an asymptotic manner. For input VIN, at t = T = loge(2)RC, V = VIN/2, at t = 2T, V = VIN/4, at t = 3T, V = VIN/8, and so on.

Engineers may be less familiar with the behavior of the same RC topology when an active circuit that synthesizes a negative resistance replaces R, but it is just as simple. A positive RC time constant can be created when the resistor R is replaced with –R. This creates a divergence exponent, VINe+t/RC.

The waveform does not converge to zero, but diverges to infinity in theory. When t=T, V=2VIN, when t=2T, V=4VIN, when t=3T, V=8VIN, and so on. Therefore, after starting the "negative discharge", VIN can be amplified by waiting for an appropriate time (t = log2(V/VIN). Divergence exponent and negative time constant are the core concepts of the circuit in Figure 2.

The amplifier gain can be programmed with a pulse width modulation (PWM) signal generated by a microcontroller or other circuit. When the PWM signal reaches a logic 0, the sample-and-hold capacitor C1 charges to VIN. When the PWM signal cycles to a logic 1, op amp A1 drives the R1C1 positive feedback loop, creating a negative time constant.

As long as the PWM signal remains at logic 1, the divergent exponential rise that causes C1 to charge continues. This creates a net voltage gain of VOUT(t) = VIN2(t/10?s + .5). Therefore, gain = 2(t/10?s + .5), log(gain) = 3 + 0.6 dB/?s. At the end of the amplification cycle, the PWM returns to logic 0 and amplifier A2 captures and holds the amplified VIN.

The logarithmic relationship between gain and timing provides excellent gain resolution, even with only 8-bit PWM signal resolution, and programmable gain is better than 0.2 dB/LSB_step over a wide range.

The timing accuracy and repeatability of the exponential signal, ADC sampling, jitter, and RC time constant stability all limit the gain programming accuracy of the amplifier. In Figure 2, a 1 ns timing error or jitter results in a 0.007% gain programming error. Fortunately, microcontrollers and data acquisition systems almost universally include programmable timer/counter hardware, which often facilitates the digital generation of repeatable PWM control signals.