Low power consumption test method for manufacturing process

Driven by the proliferation of wireless and power-efficient devices and the need to provide “green” electronic systems, designers are increasingly turning to low-power designs to address the growing challenges of functional power consumption. Until recently, managing power during manufacturing test was a secondary concern for the industry. However, as device physical sizes continue to shrink and voltage thresholds continue to decrease, there is a growing recognition that excessive power consumption during test can affect the reliability of digital ICs and lead to power-induced faults, premature failures, and errors during final test. These phenomena require special power management and low-power design techniques for manufacturing test.

Functional Mode vs. Test Mode

Several studies have shown that the test mode power consumption of deep submicron devices is several times higher than that of functional mode. Although the typical test mode power consumption limit is usually about 2 times the functional power consumption, the actual power consumption is much higher due to a variety of reasons.

For example, to reduce tester cost, multiple modules are sometimes tested simultaneously, but in functional operation, it is unlikely that many modules will work simultaneously. Switching in logic circuits during scan and high switching rates during scan/capture also result in high power consumption. Similarly, fast capture pulses in transition test waveforms can cause unwanted peak power pulses, resulting in IR drop issues. In addition, increasing the frequency of scan transfer cycles to shorten test time can also cause excessive power consumption on the tester.

Other reasons why the test power consumption value is different from the functional power consumption include field testing requirements for worst-case functional power consumption, burn-in testing, and high-voltage testing of devices. All of these operations will cause voltage and temperature increases, which may have a negative impact on the test results and the low-power circuit of the device.

In any method of reducing test power consumption, the impact on test coverage must be small and the impact on automatic test waveform generation (ATPG) tools and processes must be minimized. Similarly, the amount of test data and test time should not be significantly affected. In addition, reducing test mode power consumption too much may also result in insufficient circuit stress and affect test quality, so this situation should be avoided. Finally, the strategy adopted must not affect physical design factors such as area, power and functional timing, and must not affect the development schedule.

DFT Technology: Q Output Gating and Scanning Division

Two common power management techniques are Q output gating and low-power scan partitioning. In Q output gating, gating logic is intelligently inserted at the Q output of critical scan flip-flops to minimize switching activity in the combinational circuits during scan transfer. The gating logic is controlled by a test signal and is not activated during the capture cycle and normal functional mode. During scan transfer operations, Q output gating can reduce the switching activity that propagates through the scan flip-flops to the combinational logic. It is important to only gate registers that have a large impact on scan mode power reduction but have little impact on the critical timing paths in the design.

Scan partitioning is another design for testability (DFT) technique for managing test power consumption. By inserting DFT logic, each scan chain is divided into multiple segments, and when test data is loaded/unloaded from a scan segment, the clocks connected to all other segments can be turned off to reduce power consumption. Low-power scan partitioning has been implemented in some commercial designs, such as the CELL processor used in gaming systems.

Another related DFT technique to reduce test power consumption is data gating, which loads a constant value to scan chains in the design area that is not currently being tested. Necessary test points are inserted to load the idle chains with zero values, thereby reducing switching activity, while the active chains are loaded with data from the tester.

DFT Technique: Disable Output Drivers

Output drivers typically consume many times more power when switching than the internal logic. Avoiding output driver switching as much as possible is important for managing average power, instantaneous power, and IR drop. The main idea is to keep all tri-state output drivers in a disabled (high impedance) state during any test mode clock pulse. This approach can be applied to capture and scan transfer clocks. This can be achieved by using one or more control input signals to force the drivers to high impedance when the signal is asserted. All drivers except the activated scan output pins should be disabled during scan transfer.

Chip manufacturers often develop chips with thousands of signal I/O pins, and most of these pins may be outputs or bidirectional pins. With so many tri-state output pins, it is important to avoid simultaneous switching operations, even in the absence of clock pulses. When a large number of drivers are disabled by a single control signal, this can cause too many drivers to turn on, with corresponding spikes in current demand and voltage drop. This can be avoided by using more than one driver disable control signal, or by running the control signals through staggered delays. Careful use of DFT insertion and ATPG of such driver disable control signals is an important consideration in all low-power test methods. [page]

In addition to DFT methods, commercial ATPG tools now allow for power-aware test waveform generation. ATPG patterns are targeted at one or a group of faults during pattern generation. Waveforms that do not conflict with the control state can be merged into a unified waveform, which is called waveform compression. When compression is completed, typically less than 3% of the control points will contain specific values ​​that determine the test for the target fault. These determined control points are called care bits. The remaining control points (called non-care bits) can be filled with default random logic numbers. These random values ​​can occasionally be used to test faults that are not targeted by the waveform.

This random value filling of the non-care bits will cause about 50% of the design scan triggers to switch during scan. Commercial ATPG tools provide power management techniques that have waveform generation capabilities that adjust the default random fill. The repetitive filling method repeats the last care bit until another care bit is encountered, ensuring that the switching during scan transfer loading is greatly reduced. The same fault coverage can be achieved regardless of which method is used.

For example, if the ATPG pattern is 0XXXX110XXXX11XXXX11, where X represents a don’t care bit, then random fill may result in the final waveform being 01010110101011010111, while repeated fill becomes 011111101111111111111. Random fill has 15 toggles, while repeated fill has only 3 toggles, so the toggle rate during scan chain transfer is significantly reduced. To avoid reducing the switching action too much, another approach is to increase the switching action by adding random bits before applying repeated fill to the remaining bits. Some ATPG tools provide more automated control over the waveform to avoid understressing the IC.
Power Device Testing

To address power consumption during functional operation, many architectural-level power management techniques, including multiple voltage (MSV) and power shut-off (PSO), are becoming more widely used. Such techniques can provide up to 80% dynamic power reduction and several orders of magnitude leakage power reduction. These designs have multiple power modes, and different areas of the design (also called domains) can be in different power modes.

From a DFT perspective, when test structures such as internal scan chains, test compression, memory BIST, etc. are inserted into such a design, they must be able to operate in the target power mode. When testing the chip in the test mode corresponding to the power mode, the test structure and the controller macros that implement and maintain different power modes should be fully controllable on the tester.

Many traditional test solutions “don’t care” about these low-power features and test with all domains powered on. In a power-aware test approach, the functional power modes of the design are mapped to ATPG test waveforms. The mapping must include at least one instance of each power domain in the “on” state, which allows targeting active logic faults while testing power domain isolation logic and performing “on state” verification. Likewise, at least one instance of each power domain in the “off” state needs to be included for verification and test generation.

Another consideration is testing the power device structure, including power controllers, power switches, and state retention (SR) flip-flops, as well as structures for functional power management. During manufacturing test, defects in these low-power devices must be accurately modeled and tested. For example, traditional structural test is not sufficient to test the logic that supports power shutdown and mode transitions because traditional ATPG and fault models are not sufficient to address logic problems that are powered off. For example, after turning off power to a domain containing an SR cell, the SR cell may not function properly because the SR cell cannot maintain the state originally loaded. Current commercial DFT and ATPG tools support power device-aware testing.

Conclusion

The potential impact of power consumption during manufacturing test can no longer be ignored. The experience of many IC design teams has shown that good engineering planning, parallelism, and power-aware DFT, ATPG, and sign-off tools can mitigate the test power issues encountered in testing low-power architectures and components. This article highlights several practical DFT and AFPG techniques. With the rapid development of low-power electronic devices, more innovative techniques, tools, and excellent practical methods will emerge in the field of DFT and ATPG.

Table 1: Comparison of switching power during low-power scan using test waveform power management techniques and traditional scan.