Design of a high-speed data acquisition and storage system for aircraft

0 Introduction
With the development of remote sensing technology, the resolution of remote sensing images is getting higher and higher. The remote sensing imaging equipment carried by aircraft is also changing from the low resolution in the past to the high resolution now. While the resolution of remote sensing imaging equipment is improved, it also puts forward higher bandwidth requirements for the data downlink link of the aircraft. The corresponding ground data receiving equipment also needs to have the ability to store and process high-speed real-time data. Similarly, in terms of test equipment, in order to perform high-speed data transmission tests on large-capacity storage devices, the corresponding ground detection equipment should also have the function of high-speed data output. Therefore, it is urgent to develop a high-speed data acquisition and storage system with high-speed real-time data reception and high-speed data output functions.
From the current technical indicators of such systems, data reception and data output functions can often only reach 100Mbps to 150Mbps. According to current application requirements, the data transmission rate of high-speed data streams is often above 200Mbps or even 300Mbps. For such high-speed data streams, it is difficult for the current system to store and process them continuously and without errors. Often, because the data transmission rate exceeds the limit that the system can handle, it will cause data loss or abnormal system function and unstable state.
The design goal of the high-speed data acquisition and storage system introduced in this article is to receive and store data streams with a transmission rate of up to 300Mbps without error, and to achieve high-speed data stream output of up to 300Mbps, so as to facilitate the detection of large-capacity storage devices.
1 System Overview
The high-speed data acquisition and storage system is implemented on a 32-bit computer system, and data transmission is also completed using a 32-bit, 33MHz PCI bus. Data storage is achieved using a RAID0 disk array composed of two SATA interface hard disks. The core of the entire system is the data transmission interface card, which completes the transmission of external data to the computer memory. Then the running driver program stores the data in the memory on the hard disk. Therefore, the design of the entire system is divided into two parts: the design of the data transmission interface card and the design of the driver and application program.
2 Data transmission interface card design
The data transmission interface card is functionally divided into six modules: PCI bus interface, storage buffer, interrupt module, transmission control module, buffer control and DMA control, as shown in Figure 2-1. When working on data input, the transmission control module starts the transmission according to the buffer situation. During the transmission process, the buffer control module reads the data and sends it to the PCI bus. The DMA control module controls the data transmission on the PCI bus. After the transmission is completed, the interrupt module sends an interrupt signal to prompt the driver to process the data transferred to the memory. The following mainly introduces the design of several core modules: PCI bus interface module, DMA control module, storage buffer module and transmission control module.

2.1 Design of PCI bus interface module
The main work of PCI bus interface module is decoding PCI bus commands and latching addresses and data. The common method to implement PCI interface is to use ready-made PCI bus interface protocol chips (PLX905X series, etc.). For example, the design of data acquisition board in reference [2] adopts this method. However, since these protocol chips are often not specially developed for space applications, this design scheme cannot be adopted from the perspective of reliability. In this scheme, the design of the entire interface is implemented based on the IP core (IP Core) of LogiCORE PCI v3.0 provided by Xilinx. LogiCORE PCI v3.0 is an IP core provided by Xilinx for PCI bus interface design. Based on it, PCI bus interface can be easily customized and implemented according to the needs of actual applications. Since the IP core itself implements the decoding of configuration space and bus commands and the latching of addresses, designers only need to focus on the design of PCI transmission state machine and local control signals. Although this implementation is more complicated than directly using a dedicated chip for the PCI interface, the entire design can be integrated into a high-reliability FPGA, thereby effectively improving the reliability of the entire design.
2.2 Design of DMA control module
In order to meet the needs of high-speed data transmission and not occupy the CPU during data transmission, DMA must be used to transmit data. Since DMA transmission on the PCI bus is completed through the DMA control function of the PCI device itself, rather than relying on a separate DMA control device on the bus, the DMA control module must be implemented during the design. The DMA control module issues control commands and updates addresses during the data transmission cycle. The transmission address control can be implemented by relying on a set of transmission address registers, and the transmission control can generate control signals through the signals given by the PCI transmission state machine.
2.3 Design of storage buffer module
In order to ensure continuous and uninterrupted data transmission, only half of the buffer data is transmitted each time, and external data is always switched between the two half-areas for storage, so there will be no data loss or discontinuity. [page]

The timing of a typical write data transfer on a PCI bus is shown in Figure 2-2. First, the data to be transferred must be read out from the local buffer in advance, and then appear on the bus AD signal line. When the IRDY signal and TRDY signal are both valid (at a low level), they are acquired by the target device. When the transfer is completed, the last data pre-read from the local buffer (shaded data 3 in the figure) will not be transferred to the target device. The local buffer control module will think that the data has been transferred. If no measures are taken at this time, data loss will occur.

At the end of the transmission, the PCI bus transmission state machine switches to the state of backing up data. In this state, the buffer control module will detect whether there is data that has been read but not transmitted. If so, the control module will take measures to prevent data loss. For the storage structure of dual-port RAM, after the data is read, as long as the data is not written at the same address, the data will not be lost. Therefore, to implement the previous function, you only need to simply modify the address currently pointed to by the read pointer.
2.4 Design of the transmission control module
The core of the transmission control module is a transmission control state machine. It controls the transmission by detecting the status of the storage buffer. When the data in the input buffer is full or the output buffer is empty, it automatically requests a data transmission, thereby ensuring the continuity of the data flow.
3 Driver and application development
The driver is developed using the standard WDM (Windows Driver Model) device driver model and the driver development toolkit of DriverStudio. Regarding the WDM driver model, due to space limitations, it will not be introduced in detail.
A typical data transmission process is carried out as follows. First, the driver completes the initialization of the device, such as opening a buffer in the memory, initializing the hardware device, etc. After the initialization is completed, the hardware is in a state of waiting for transmission. When the user issues a data transmission instruction through the application, the driver processes the request and issues an instruction to the hardware to start data transmission. Since the data transmission time may be relatively long, the application adopts a multi-threaded design. The transmission thread will wait for the signal sent by the driver at the end of the transmission, while the application can also complete the interaction with the user. When the transmission is completed, the driver writes a stop instruction to the hardware to terminate the transmission and sends a transmission end signal to the application. The driver communicates with the application by creating Win32 events.
4 Simulation and verification of the design
In order to verify the correctness of the design, it is first necessary to simulate the logical function of the design. In order to verify whether the design can work normally on the PCI bus, it is necessary to simulate various bus transactions on the PCI bus and verify whether the design can respond to various bus commands. The simulation is implemented based on the PCI bus interface simulation example provided by Xilinx. A simple bus arbitrator is designed according to the PCI bus specification to simulate the process of the master device applying for bus occupation. In addition, a slave device on the PCI bus is designed to simulate the data transmission process between the master device and the slave device. In addition, the automatic configuration process of the device on the bus is simulated. By observing the simulation waveform, it is found that the design fully meets the data transmission specifications of the PCI bus, and the data transmission results are correct.
On the basis of the simulation verification, the design is implemented in the FPGA of Xilinx company model virtexII2v1000-fg456-5. The data interface card is installed on the test computer, and the system is verified and performance tested by using the self-loop data transmission function and unidirectional input and output function of the data interface card. The results are shown in Table 1.
It can be seen from the results that when the input and output rate is kept below 160Mbps, the self-loop data transmission can be guaranteed to be error-free, but when the rate is increased to 200Mbps, data loss will occur in the transmission, resulting in inconsistency between the received data and the sent data. Therefore, in order to ensure error-free data transmission, the self-loop data transmission test rate should not be higher than 160Mbps.

In the unidirectional input and output test, when the input rate or output rate is less than 300Mbps, the system function is completely correct, but when it works at 400Mbps, data loss will occur. Compared with the data of the self-loop transmission test, it can be seen that when the self-loop data transmission test rate is 200Mbps, since the system receives and outputs at the same time, the bus is shared, which is equivalent to the transmission rate of 400Mbps when receiving or outputting alone. The consistency of the two test results also shows the reliability of the test.
5 Conclusion
Through the test and verification of the system, it is proved that this design can fully meet the requirements of high-speed real-time data flow for data acquisition and storage systems. In order to facilitate further work in the future, a simple test was also conducted on the relationship between the buffer size and the transmission rate during the test. After changing the buffer size from 8KB to 16KB, the transmission rate is only slightly improved, and the improvement in performance is not obvious. The results show that simply expanding the hardware buffer will not bring about a significant improvement in the data transmission rate, and will also occupy the valuable RAM resources inside the FPGA. The reason is that the data transfer rate is mainly limited by the 32-bit/33MHz PCI bus bandwidth itself and the peak hard disk read and write rate, rather than the buffer size. It can be predicted that if a 64-bit/66MHz PCI bus is used and more disks are used to form a RAID disk array to increase the disk read and write rate, the overall performance will be greatly improved.