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FPGA Resource Special Topic (I) Book Summary

Why should we learn FPGA? Since its birth, FPGA has experienced a transformation from a supporting role to a leading role. FPGA is mainly used to replace complex logic circuits. Now the focus is on the platform concept. When integrated with digital signal processors, embedded processors, high-speed serial and other high-end technologies, it is applied to more fields. Because of its rapid development, more people who learn FPGA see hope. Its broad prospects are one of the reasons why we choose it. (1) Broad development prospects 2) More employment opportunities (3) Greater space for technological development 3. How to learn FPGA? (1) Mastering FPGA programming language (2) An easy-to-learn and easy-to-use hardware platform is half the battle (3) Consolidation and sublimation of technology In summary, only after we understand what FPGA is, why we should learn FPGA, and how to learn FPGA, can we learn and master this technology in a very purposeful and planned way. Based on the above, we have sorted out this FPGA series of topics with the aim of helping everyone collect more FPGA learning resources so that everyone can spend less effort and get more learning opportunities.

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《A Classic FPGA Book》: Points it Requires : 1 Type:Application DocumentsUploader:adminDate:2012-12-09; Introduction:A good book, worth reading. The specific files include: \"A Classic FPGA Book\" and the corresponding schematic diagram. Content introduction: Taking Xilinx\'s FPGA as an example, the article introduces the concept of FPGA and the configuration circuit, and then introduces the construction of the software environment, programming language learning, hardware-oriented development thinking and actual application development examples.

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\"Mastering FPGA in Simple Terms\" HD Bookmark Edition: Points it Requires : 1 Type:Technical DocumentationUploader:chen8710Date:2013-05-11; Introduction:\"A Simple and Easy Way to Play with FPGA\" HD Bookmark Edition Author: Wu Houhang (Net Name: Quanyou Tongxue) Publication Date: May 2010 Introduction: This book collects the author\'s experience in FPGA learning and events. The book contains daily learning notes, in-depth discussions on some common design techniques and methods, and many vivid case analyses. Most of these cases are based on specific engineering projects and have certain reference value. There are also some experimental routines suitable for beginners and advanced learning. In addition, two relatively complete DIY projects are given to allow readers to understand the FPGA development process from a system perspective. This book is triggered by engineering practice and aims to lead readers to learn how to find, analyze and solve problems in FPGA development and design. The CD attached to this book contains a large number of practical routines. The main readers of this book are students majoring in electronics, computers, control and information, electronic engineers engaged in FPGA/CPLD development and design, and all electronic design and production enthusiasts.

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Xilinx ISE FPGA Development Practical Tutorial Tian Yun Tsinghua University: Points it Requires : 1 Type:Application DocumentsUploader:xieryouDate:2013-06-28; Introduction:Xilinx is the earliest and largest FPGA manufacturer. Its chip design technology, development software and related solutions are at the top level in the industry and have a wide customer base. This book mainly describes the development knowledge of Xilinx FPGA, including FPGA basics, Verilog HDL language basics, HDL language advanced based on Xilinx chips, ISE development environment usage guide, FPGA configuration circuit and software operation, use of online logic analyzer ChipScope, FPGA-based digital signal processing technology, SystemGenerator-based DSP system development technology, FPGA-based programmable embedded development technology, FPGA-based high-speed data connection technology, and timing analysis principles and the use of timing analyzers. These 11 chapters cover the main aspects of FPGA development. It is hoped that this book can improve readers\' engineering development capabilities. This book systematically describes the development knowledge of Xilinx FPGA, including an introduction to FPGA development, the basics of Verilog HDL language, advanced HDL language based on Xilinx chips, a guide to using the ISE development environment, FPGA configuration circuits and software operations, the use of the online logic analyzer ChipScope, digital signal processing technology based on FPGA, DSP system development technology based on SystemGenerator, programmable embedded development technology based on FPGA, high-speed data connection technology based on FPGA, timing analysis principles, and the use of timing analyzers. The book covers 11 chapters, each of which is based on examples and covers the main aspects of FPGA development. This book is suitable for engineers engaged in the design and development of Xilinx series FPGAs, as well as graduate students and senior undergraduates in related majors. Chapter 1 Introduction to FPGA Development 1.1 Basics of Programmable Logic Devices 1.1.1 Overview of Programmable Logic Devices 1.1.2 History of Programmable Logic Devices 1.1.3 PLD Development Tools 1.2 FPGA Chip Structure 1.2.1 FPGA Working Principle and Introduction 1.2.2 FPGA Chip Structure 1.2.3 Concepts of Soft Core, Hard Core and Solid Core 1.3 Development Process Based on FPGA 1.3.1 Overview of FPGA Design Method 1.3.2 Typical FPGA Development Process 1.3.3 FPGA-Based SOC Design Method 1.4 Introduction to Xilinx\'s Mainstream Programmable Logic Devices 1.4.1 Introduction to Xilinx FPGA Chips 1.4.2 Introduction to Xilinx PROM Chips 1.5 Summary of this Chapter Chapter 2 Basics of Verilog HDL Language 2.1 Introduction to Verilog HDL Language 2.1.1 History of Verilog HDL Language 2.1.2 Main Capabilities of Verilog HDL 2.1.3 Differences between Verilog HDL and VHDL 2.1.4 Verilog HDL Design Method 2.2 2.3.1 Verilog HDL basic program structure2.3.2 Verilog HDL language data types and operators2.3.1 Identifiers2.3.2 Data types2.3.3 Module ports2.3.4 Constant sets2.3.5 Operators and expressions2.4 Verilog HDL language description statements2.4.1 Structural description form2.4.2 Data flow description form2.4.3 Behavioral description form2.4.4 Mixed design mode2.5 Verilog code writing standards2.5.1 Signal naming rules2.5.2 Module naming rules2.5.3 Code format standards2.5.4 Module call standards2.6 Verilog common program examples2.6.1 Verilog basic modules2.6.2 Basic timing processing modules2.6.3 Verilog implementation of common digital processing algorithms2.7 Chapter summaryChapter 3 Advanced HDL language based on Xilinx chips3.1 Design thinking for hardware circuits3.1.1 Hardware-oriented programming thinking3.1.2 Principles of conversion between “area” and “speed”3.1.3 Design principles of synchronous circuits3.1.4 Design principles of module division3.2 Excellent HDL coding style3.2.1 Meaning of coding style3.2.2 Introduction to general coding style3.2.3 *Brief description of coding style3.3 Verilog modeling and debugging skills3.3.1 Use and simulation of bidirectional ports3.3.2 Blocking assignment and non-blocking assignment3.3.3 Combinational logic circuits with uncertain input values3.3.4 Bit expansion and truncation operations in mathematical operations3.3.5 Using block RAM to achieve data delay3.3.6 Test vector generation3.4 How to use Xilinx primitives3.4.1 Computing component3.4.2 Clock component3.4.3 Configuration and detection component3.4.4 Gigabit transceiver component3.4.5 I/O port component3.4.6 Processor component3.4.7 RAM/ROM component3.4.8 3.4.9 Registers and Latches 3.4.10 Slice/CLB Components 3.5 Summary of this Chapter Chapter 4 ISE Development Environment User Guide Chapter 5 FPGA Configuration Circuit and Software Operation Chapter 6 Using the Online Logic Analyzer ChipScope Chapter 7 Digital Signal Processing Technology Based on FPGA Chapter 8 DSP System Development Technology Based on System Generator Chapter 9 Programmable Embedded Development Technology Based on FPGA Chapter 10 High-Speed Data Connection Technology Based on FPGA Chapter 11 Timing Analysis Principles and the Use of Timing Analyzers Abbreviations References

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FPGA embedded project development trinity practical teaching: Points it Requires : 1 Type:Technical DocumentationUploader:shimmy_leeDate:2014-12-30; Introduction:The book is based on the project background and introduces the methods and techniques of FPGA embedded project development in an easy-to-understand way through a large number of examples. The book is divided into 17 chapters. Chapters 1 to 3 are basic development knowledge, which briefly introduce FPGA chips, programming languages and common development tools to guide readers to get started with technology; Chapters 4 to 17 are application examples. Through 14 examples, the development principles, process ideas and techniques in the fields of FPGA industrial control, multimedia applications, consumer electronics and network communications are elaborated in detail. All examples come from engineering practice, which are representative and instructive. After learning, readers can learn from one example and improve their design level rapidly, completing the technical leap from entry to mastery. This book is rich in content, reasonable in structure and typical in examples. It not only introduces the hardware design and software programming of FPGA embedded in detail, but also provides perfect design ideas and solutions, summarizes the development experience and precautions, and makes detailed comments on the program code of the example, so that readers can understand the essence, learn thoroughly and apply what they have learned quickly. This book is equipped with a CD, which contains the hardware schematics, program codes and audio and video explanations of the development process of all the examples in the book, so that readers can further consolidate and improve. This book is suitable for college students majoring in computer science, automation, electronics, hardware, etc., as well as scientific researchers engaged in FPGA development.

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FPGA/CPLD Design Tool - Detailed Introduction to Xilinx ISE 378 pages 71.7M: Points it Requires : 1 Type:Technical DocumentationUploader:tywDate:2013-12-09; Introduction:FPGA/CPLD Design Tool - Detailed Introduction to Xilinx ISE 378 pages 71.7M

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Xilinx University Program designated textbook - FPGA digital signal processing implementation principles and methods - original first release: Points it Requires : 2 Type:CourseUploader:空气Date:2013-06-09; Introduction:Perfect and clear bookmark version PDF e-book, original Internet first release Introduction This book comprehensively and systematically introduces the principles and methods of digital signal processing based on FPGA. The book includes 12 chapters and 11 experiments. The main contents include introduction to digital signal processing design, hardware structure and operation function of FPGA, overview of signal and its processing theory, principle and implementation of Cordic algorithm, design of FIR filter and IIR filter, design of other commonly used digital filters, retiming signal flow chart, principle and implementation of digital communication signal processing, theoretical basis of adaptive signal processing, implementation of adaptive signal processing based on FPGA, principle and implementation of signal synchronization, implementation and experiment of digital signal processing based on acceldsp. This book refers to a large number of the latest design materials, with novel content, equal emphasis on theory and application, and fully reflects the latest methods and technologies for digital signal processing based on FPGA, which can help readers master these methods and technologies systematically. This book can be used as a teaching reference book for undergraduates and postgraduates who have opened FPGA digital signal processing courses in related majors, as well as a self-study reference book for teachers, postgraduates and scientific and technological personnel engaged in FPGA digital signal processing research, and as a training book for related courses of Xilinx. Contents Chapter 1 Introduction to Digital Signal Processing Design 1 1.1 Overview of Digital Signal Processing Technology 1 1.1.1 Development of Digital Signal Processing Technology 1 1.1.2 Classification of Digital Signal Processing Algorithms 3 1.1.3 Implementation Methods of Digital Signal Processing 4 1.2 Implementation of Digital Signal Processing Based on FPGA 5 1.2.1 Structural Characteristics of FPGA 5 1.2.2 Common Resources of FPGA 7 1.2.3 Digital Signal Processing Process Based on FPGA 10 1.3 Implementation of Digital Signal Processing Based on DSP 14 1.3.1 Structural Characteristics of DSP 14 1.3.2 Running Code and Performance of DSP 16 Chapter 2 Hardware Structure and Computational Functions of FPGA 19 2.1 Internal Structure and Functions of Virtex-II 19 2.1.1 Logic Resources of Virtex-II 19 2.1.2 Registers and Pipelines 21 2.1.3 Virtex-II RAM Resources 22 2.1.4 Virtex-II Embedded Multiplier 23 2.1.5 2.1.1 Virtex-5 Platform Architecture 2.1.2 Virtex-5 Logic Resources 2.1.3 DSP48E Slice Structure and Function 3.1.4 DSP48E Filter Design 4.1.5 FPGA-Based Digital Representation 5.1.1.2 Representation of Integers 5.1.2 Representation of Non-Integer Values 5.1.3 Floating-Point Number Definition and Representation 5.1.4 FPGA-Based Digital Representation 6.1.1.3 FPGA-Based Digital Representation 6.1.2.3 DSP48 Slice Structure and Function 7.1.4 DSP48E Slice Design 7.1.5 DSP48E Filter Design 7.1.6 DSP48E Filter Design 7.1.7 FPGA-Based Digital Representation 8.1.1.4 FPGA-Based Digital Representation 8.1.1.5 FPGA-Based Digital Representation 9.1.1.6 FPGA-Based Digital Representation 9.1.1.7 FPGA-Based Digital Representation 10.1.1.8 FPGA-Based Digital Representation 10.1.1.9 FPGA-Based Digital Representation 11.1.10 3.4 Noise and its processing 83 3.4.1 Definition and representation of noise 83 3.4.2 Intrinsic noise level 84 3.4.3 Noise/distortion chain 85 3.4.4 Definition and representation of signal-to-noise ratio 85 3.4.5 Signal extraction method 86 3.5 Analog signal and processing 87 3.5.1 Processing of analog I/O signals 87 3.5.2 Processing of analog communication signals 87 3.6 Digital signal and processing 88 3.6.1 General input and output DSP system 88 3.6.2 Signal conditioning 89 3.6.3 Analog-to-digital converter ADC and quantization effect 92 3.6.4 Digital-to-Analog Converter DAC and Signal Reconstruction 97 3.6.5 Definition and Measurement of SFDR 100 3.7 Software Processing of Communication Signals 100 3.7.1 Definition of Software Radio SR 100 3.7.2 Software Radio Implementation of IF 101 3.7.3 Channelization Process 102 3.7.4 Base Station Software Radio Receiver 102 3.7.5 SR Sampling Technology 103 3.7.6 Direct Digital Down Conversion 104 3.7.7 Solution to Bandpass Sampling Failure 104 Chapter 4 CORDIC Algorithm Principle and Implementation 107 4.1 Introduction to CORDIC 107 4.2 CORDIC Algorithm Principle 107 4.2.1 Circular Coordinate System Rotation 107 4.2.2 Linear Coordinate System Rotation 112 4.2.3 Hyperbolic Coordinate System Rotation 112 4.2.4 General Description of CORDIC Algorithm 113 4.3 4.3.3 Analysis of Rounding Error 115 4.3.4 Estimation of the Significant Bit (deff) 116 4.3.5 Prediction and Simulation 116 4.4 Implementation of CORDIC Algorithm Based on System Generator 117 4.4.1 Implementation of CORDIC Loop Structure 117 4.4.2 Implementation of CORDIC Non-loop Structure 119 4.4.3 Implementation of CORDIC Non-loop Pipeline Structure 119 4.4.4 Performance Comparison of Three Implementation Methods 119 Chapter 5 Design of FIR Filters and IIR Filters 122 5.1 Conversion from Analog to Digital Filters 122 5.1.1 Approximation of Differential Equations 122 5.1.2 Bilinear Commutation 123 5.2 Types of Digital Filters 124 5.3 Design of Basic Digital FIR Filters 125 5.3.1 Characteristics of FIR Filters 125 5.3.2 Design Rules of FIR Filters 132 5.4 Design of Digital IIR Filters 135 5.4.1 Principle of IIR Filters 135 5.4.2 Model of IIR Filters 135 5.4.3 Analysis of IIR Filters in the z-Domain 136 5.4.4 Performance and Stability of IIR Filters 137 Chapter 6 Design of Other Common Digital Filters 140 6.1 Design of Moving Average Filters 140 6.1.1 Principle of Moving Average 140 6.1.2 Eight-Weight Moving Average 140 6.1.3 Nine-Weight Moving Average 142 6.1.4 Transposed Structure of Moving Average 142 6.2 Design of Differentiator and Integrator 143 6.2.1 Spectral Characteristics of Differentiator 143 6.2.2 Spectral Characteristics of Integrator 143 6.3 Design of Comb Filter 145 6.4 Design of Integrator Comb Filter 145 6.5 Generation and Demodulation of IF Modulated Signal 148 6.5.1 Generation of IF Modulated Signal 148 6.5.2 Demodulation of IF Modulated Signal 149 6.5.3 CIC Extraction to Extract Baseband Signal 150 6.5.4 Attenuation and Correction of CIC Filter 152 6.6 Implementation of CIC Filter 153 6.7 Determining the Bit Width of CIC Filter 155 6.7.1 Determining the Bit Width of CIC Decimation Filter 155 6.7.2 Determining the Bit Width of CIC Insertion Filter 157 6.8 Sharpening of CIC Filter 157 6.8.1 Characteristics of SCIC Filter 157 6.8.2 Characteristics of ISOP Filter 160 6.9 Recursive and Non-recursive Structures of CIC Filter 163 Chapter 7 Retiming Signal Flow Graph 168 7.1 7.1.1 Signal Flow Graph Critical Path 168 7.1.2 Signal Flow Graph Delay 169 7.2 Cut-Set Retiming and Rules 169 7.2.1 Cut-Set Retiming Concept 169 7.2.2 Cut-Set Retiming Rules 1 1 70 7.2.3 Cut-Set Retiming Rules 2 1 72 7.2.4 Two Types of FIR Retiming SFG 176 7.3 Systolic Arrays 181 7.3.1 Introduction to Systolic Arrays 181 7.3.2 FIR Filter Systolic Arrays and Retiming 182 7.3.3 IIR Filter Systolic Arrays and Retiming 188 7.4 SFG of Adaptive Filter 191 Chapter 8 Principles and Implementation of Digital Communication Signal Processing 193 8.1 Signal Detection Theory 193 8.1.1 Histogram Representation of Probability 193 8.1.2 Probability Density Function 194 8.2 Binary Baseband Data Transmission 196 8.2.1 Pulse Shaping 196 8.2.2 Baseband Transmission Signal Reception Error 198 8.2.3 Application of Matched Filters 200 8.3 Signal Modulation Technology 203 8.3.1 Channel and Bandwidth 203 8.3.2 Signal Modulation Technology 204 8.3.3 Transmission of Digital Signals 221 Chapter 9 Theoretical Basis of Adaptive Signal Processing 223 9.1 Background of Adaptive Signal Processing Technology 223 9.2 Structure of Adaptive Signal Processing System 224 9.2.1 Structure of General Signal Processing System 224 9.2.2 Indicators of Digital FIR Filter 224 9.2.3 9.2.4 Adaptive Digital Signal Processing Architecture 226 9.2.5 Analog Interface 227 9.2.6 Different Architectures of Adaptive Signal Processing 227 9.3 Applications of Adaptive Signal Processing 228 9.3.1 Channel Identification 228 9.3.2 Echo Cancellation 229 9.3.3 Acoustic Echo Cancellation 230 9.3.4 Power Line AC Noise Suppression 231 9.3.5 Background Noise Suppression 231 9.3.6 Channel Equalization 232 9.3.7 Adaptive Spectral Line Enhancement 233 9.4 Adaptive Signal Processing Algorithms 233 9.4.1 Mean Square Error Minimization Algorithm 234 9.4.2 LMS Algorithm 237 9.4.3 RLS Algorithm 241 9.4.4 Active Noise Control 246 Chapter 10 Implementation of Adaptive Signal Processing Based on FPGA 247 10.1 LMS Hardware Implementation Architecture 247 10.1.1 Principles of LMS Hardware Implementation Structure 247 10.1.2 Serial LMS Structure 248 10.1.3 Retimed SLMS Structure 249 10.1.4 Non-standard LMS (NCLMS) Structure 250 10.1.5 Pipeline LMS Structure 251 10.1.6 Look-ahead Technique 253 10.1.7 PIPLMS Structure 254 10.1.8 PIPLMSK Structure 255 10.1.9 PIPLMS1 Structure 255 10.1.10 DLMS Structure 256 10.1.11 ALMS Structure 257 10.1.12 Complex LMS 257 10.1.13 Comparison of RLS and LMS Techniques 259 10.2 Calculation of Least Squares Solution 260 10.2.1 Principles of Least Squares Calculation 260 10.2.2 Least Squares Calculation 261 10.2.3 Recursive Least Squares Algorithm 262 10.3 Exponential RLS Algorithm Implementation 263 10.3.1 Exponential RLS Algorithm Principle 263 10.3.2 Exponential Recursive Least Squares 263 10.4 QR-RLS Algorithm Principle and Implementation 264 10.4.1 QR Decomposition of RLS 264 10.4.2 Solution of RLS QR 265 10.4.3 Implementation of QR Decomposition 265 10.4.4 FPGA Implementation of QR Algorithm 266 10.4.5 Three-Array Method of QR-RLS 267 Chapter 11 Signal Synchronization Principle and Implementation 269 11.1 Signal Synchronization Problem 269 11.2 Signal Timing and Timing Recovery 270 11.2.1 Signal Timing Principle 270 11.2.2 Signal Timing Recovery 270 11.2.3 Carrier Phase Offset and Control 274 11.2.4 Principle of Frame Synchronization 278 11.2.5 Digital Down-Conversion 279 11.2.6 Principle and Implementation of Digitally Controlled Oscillator 280 11.2.7 Synchronization of BPSK Received Signal 282 Chapter 12 Implementation of Digital Signal Processing Based on AccelDSP 285 12.1 AccelDSP Software Design Process 285 12.1.1 Overview of AccelDSP Software Functions 285 12.1.2 AccelDSP Synthesis Process 285 12.2 Design Implementation Based on AccelDSP 289 12.2.1 Design Principle 289 12.2.2 Create Project 290 12.2.3 M Code Writing 291 12.2.4 Verify Floating-Point Model 294 12.2.5 Generate Fixed-Point Model 295 12.2.6 Verify Fixed-Point Model 296 12.2.7 Floating point and fixed point comparison 297 12.3 RTL model 297 12.3.1 Generation of RTL model 297 12.3.2 Verification of RTL model 299 12.3.3 Synthesis of RTL model 299 12.3.4 Implementation process 300 12.3.5 Verification of gate-level netlist 301 12.4 Using System Generator process 301 Experiment 1 Use of System Generator software tool 303 1.1 Experimental purpose 303 1.2 Experimental environment 303 1.3 Introduction to software use 303 1.3.1 Connection between System Generator and MATLAB software 303 1.3.2 Functions of Xilinx tool modules 304 1.4 Experimental principle 305 1.5 Experimental steps 306 1.5.1 Setting method and function of each module parameter in the project 306 1.5.2 Setting and running specific parameters in the project 313 Experiment 2 2.1 Experimental Purpose 316 2.2 Experimental Environment 316 2.3 Experimental Principle 316 2.4 Experimental Steps 318 2.4.1 Design of Asymmetric Filter 318 2.4.2 Design of Symmetric Filter 319 2.4.3 Design of Multiplexed Filter 319 2.5 Experimental Analysis 321 Experiment 3 Design of CORDIC Algorithm 322 3.1 Experimental Purpose 322 3.2 Experimental Environment 322 3.3 Experimental Principle 322 3.4 Experimental Steps 323 3.4.1 Convergence Verification of CORDIC Algorithm 323 3.4.2 Design of CORDIC Subsystem 325 3.4.3 Design of Arithmetic Function of Circular Coordinate System 326 3.4.4 Two Design Methods of CORDIC Architecture with Pipeline Technology 327 3.4.5 Research on Vector Amplitude Accuracy 327 3.5 Experimental Analysis 328 Experiment 4 FIR Filter Design 330 4.1 Experimental Purpose 330 4.2 Experimental Environment 330 4.3 Experimental Principle 330 4.4 Experimental Procedure 332 4.4.1 Design and Comparison of Simple FIR Filters 332 4.4.2 Designing Filters Using FDATool Module 334 4.4.3 Audio Filtering on XUP Virtex-II Pro Board 338 4.5 Experimental Analysis 341 Experiment 5 CIC Filter Design 342 5.1 Experimental Purpose 342 5.2 Experimental Environment 342 5.3 Experimental Principle 342 5.4 Experimental Procedure 343 5.4.1 Design of a First-Stage CIC Filter 343 5.4.2 Design of a Multi-Stage CIC Filter 345 5.4.3 Design of CIC Interpolation and Decimation Filters 346 5.5 Experimental Analysis 347 Experiment 6 Digital Communication Signal Processing 348 6.1 6.4 Experimental steps 358 6.4.1 Design of transmitter 358 6.4.2 Design of pulse shaping and matched filter 359 6.4.3 Design of receiver 360 6.5 Experimental analysis 361 Experiment 7 Design of digital frequency converter 362 7.1 Experimental goal 362 7.2 Experimental environment 362 7.3 Experimental principle 362 7.4 Experimental steps 364 7.4.1 Design of digital up-conversion 364 7.4.2 Design of digital down-conversion 365 7.5 Experimental analysis 366 Experiment 8 Design of digital controlled oscillator 367 8.1 Experimental goal 367 8.2 Experimental environment 367 8.3 Experimental principle 367 8.4 Experimental steps 368 8.5 Experimental analysis 369 Experiment 9 9.1 Experimental Purpose 361 9.2 Experimental Environment 361 9.3 Experimental Principle 361 9.4 Experimental Procedure 362 9.4.1 Design of Pulse Shaping Using Filter 362 9.4.2 Design of Quantization and Spectrum Masking 363 9.5 Experimental Analysis 364 Experiment 10 Design of Adaptive Filter 365 10.1 Experimental Purpose 365 10.2 Experimental Environment 365 10.3 Experimental Principle 365 10.4 Experimental Procedure 366 10.4.1 Design of Standard Parallel Adaptive LMS Filter 366 10.4.2 Design of Non-standard LMS Filter 367 10.4.3 Using Configurable LMS Audio 367 10.5 Experimental Analysis 367 Experiment 11 Design of System Synchronization 368 11.1 Experimental Purpose 368 11.2 Experimental Environment 368 11.3 Experimental Principle 368 11.4 Experimental Procedure 370 11.4.1 Design of Phase-locked Loop 370 11.4.2 Design of Carrier Synchronization 371 11.5 Experimental Analysis 374 References 376

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[AltiumDesigner Practical Guide: FPGA Design] by Yan Shengli: Points it Requires : 1 Type:Technical DocumentationUploader:论文帝Date:2013-07-01; Introduction:【Author】Yan Shengli 【Publisher】 Beijing: Electronic Industry Press, 2008 【ISBN】7-121-06166-X 【Number of pages】277 【Original book price】38.00 【Chinese Library Classification Number】TN410.2 (Industrial Technology>Radio Electronics, Telecommunications Technology>Microelectronics, Integrated Circuits (IC)>Printed Circuits) 【Reference format】Yan Shengli. Altium Designer Practical Guide FPGA Design. Beijing: Electronic Industry Press, 2008. 【Abstract】 Based on the NanoBoard-NB1 developer, this book introduces in detail the complete development process of FPGA projects and embedded system projects from design to target board implementation, as well as the use of NanoBoard-NB1 developer and virtual instruments in the system. The CD-ROM that comes with this book contains the latest trial version of Altium Designer software authorized by Altium, training video tutorials and some reference materials. This book comes with a CD-ROM.

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The Definitive Guide to FPGAs: Points it Requires : 1 Type:Technical DocumentationUploader:royrukesDate:2013-11-19; Introduction:The authoritative guide to FPGA, which is helpful for people engaged in FPGA development

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FPGA Development Guide - Volumes 1 and 2 (Innovative Design Guide for Engineers): Points it Requires : 1 Type:Technical DocumentationUploader:sinceyouloveDate:2013-09-22; Introduction:Chapter 1: Why do engineers need to master FPGA development knowledge? 5Chapter 2, FPGA basic knowledge and development trend72.1 FPGA structure and working principle72.1.1 Dreams make great achievements72.1.2 FPGA structure82.1.3 The concepts of soft core, hard core and solid core152.1.4 Looking at the future trend of FPGA from the development of programmable devices15Chapter 3, FPGA major suppliers and products173.1.1 Introduction to Xilinx\'s main products17Chapter 4, FPGA basic development process294.1 Typical FPGA development process and precautions294.2 FPGA-based SOC design method32 Typical FPGA-based SOC development process32Chapter 5, FPGA practical development skills335.1 FPGA device selection common sense335.1.1 Device supply channels and development tool support335.1.2 Device hardware resources335.1.3 Electrical interface standards345.1.4 Device speed grade355.1.5 Device temperature grade355.1.6 Device packaging355.1.7 Device price 355.2 How to perform early system planning for FPGA design 365.3. Synthesis and simulation skills 375.3.1 Use of synthesis tool XST 375.3.2 ISE-based simulation 425.3.3 Settings and timing analysis related to FPGA interface 455.3.4 11 XST tips revealed by synthesis experts 515.4 Synthesis and routing problems caused by large-scale design 525.5 FPGA-related circuit design knowledge 545.5.1 Configuration circuit 545.5.2 Master-serial mode - the most commonly used FPGA configuration mode 565.5.3 SPI serial Flash configuration mode 585.5.4 Slave-serial configuration mode 625.5.5 JTAG configuration mode 635.5.6 System ACE configuration solution 645.6 Debugging experience for large-scale design 685.6.1 ChipScope Pro component application example 685.7 IP and algorithm application in FPGA design 745.7.1 IP core overview 745.7.2 FFT IP core application example 755.8 Xilinx FPGA-specific HDL development skills 795.8.1 Xilinx FPGA architecture features 795.8.2 Xilinx FPGA chip-specific code style 79ISE and EDK development skills 835.10 Introduction to the new generation development tool ISE Design Suit10.1 855.10.1 Overview of ISE Design Suit10.1 855.10.2 Innovative features of ISE Design Suit 10.1 855.11 Skills for using ISE with third-party software 925.11.1 How to use Synplify Pro software 925.11.2 How to use ModelSim software 995.11.3 The joint development process of Synplify Pro, ModelSim and ISE 1045.11.4 The joint use of ISE and MATLAB 1055.12 Conquering three challenges of FPGA low-power design 1085.13 The Path to Mastery - Advanced Routes in FPGA Design and Development 111 Appendix 1: FPGA Development Resource Summary 112 Appendix 2: Editorial Board Information and Postscript 113 Appendix 3: Copyright Statement 114

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FPGA embedded system development based on EDK: Points it Requires : 1 Type:Application DocumentsUploader:TimsonDate:2013-01-08; Introduction:This book introduces the use of Xilinx\'s embedded integrated development platform EDK tool group, FPGA embedded CPU cores - soft core Microblaze and hard core PowerFC405, as well as the process and methods of using these CPU cores and various peripheral IP cores provided by Xilinx for embedded design. It guides readers to become familiar with the EDK development environment and quickly enter the vast world of on-chip system development at a relatively low cost. Based on Xilinx\'s technical information, this book explains in a simple and easy-to-understand way how to use each component tool in the EDK tool group, the division of labor and connection between each other, the collaborative development skills of the EDK tool group and the ISE tool group, and the necessary third-party tool matching methods, showing readers a complete FPGA embedded development process based on EDK. It can be used as an introductory guide to learning Xilinx embedded development, or as a design reference manual. This book comes with a CD containing several experimental programs written by the author for this book, with content from the basic structure design to embedded Linux transplantation and other aspects. Each program includes complete source code, all intermediate generated files, and hardware burning files, all of which have been verified by the author and can be run directly. This book can be used as a reference for engineers and teachers engaged in hardware design, system development, and embedded design in the fields of electronic engineering, communications, computer science, and automatic control. It can also be used as a textbook for senior undergraduate and graduate students in related majors.

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FPGA Implementation of Digital Signal Processing 372 pages 9.6M: Points it Requires : 1 Type:Technical DocumentationUploader:tywDate:2013-12-09; Introduction:FPGA Implementation of Digital Signal Processing 372 pages 9.6M \"FPGA Implementation of Digital Signal Processing\" (2nd Edition) is a monograph on the latest digital signal processing. The book comprehensively and insightfully introduces all aspects of digital signal processing using FPGA through a large number of program examples. In terms of front-end digital signal processing algorithms, the new field programmable gate array (FPGA) is gradually replacing and, thus bringing a new revolution to digital signal processing. Therefore, the effective implementation of these algorithms is very critical, which is also the main purpose of this book.

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\"Introduction to FPGA Application Development and Typical Examples\" Posts and Telecommunications Press: Points it Requires : 1 Type:Technical DocumentationUploader:xieryouDate:2013-02-20; Introduction:书名：《FPGA应用开发入门与典型实例》作者：华清远见编著出版社：人民邮电出版社出版时间：2008-7-1 简介： FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。　　本书内容全面、实例丰富，适合FPGA系统设计初学者，大专院校通信工程、电子工程、计算机、微电子和半导体相关专业师生，硬件系统工程师和IC设计工程师学习使用。

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@@-CPLD／FPGA Common Modules and Integrated System Design Examples-452 pages-65.7M.rar: Points it Requires : 1 Type:Application DocumentsUploader:jujuyaya222Date:2014-03-05; Introduction:This book introduces the methods and techniques of CPLD/FPGA common modules and integrated application system design in detail. The book is divided into 3 parts and 22 chapters. The first part is the basic knowledge part, which briefly introduces the CPLD/FPGA hardware structure knowledge, VHDL hardware programming language, Verilog and SystemC programming, and common development tools; the second part is the common module design example part, which introduces various CPLD/FPGA development technologies and usage skills in detail through 14 module design examples. These module examples cover almost all CPLD/FPGA development technologies; the third part is the integrated system design example part, which conducts a comprehensive application design of the previous CPLD/FPGA common modules through 4 integrated system examples.

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FPGA Principles, Design and Applications 262 pages 7.5M: Points it Requires : 1 Type:Technical DocumentationUploader:tywDate:2013-12-09; Introduction:FPGA Principles, Design and Applications 262 pages 7.5M

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