XAPP854-数字锁相环(DPLL)参考设计 Many applications require a clock signal to be synchronous, phase-locked, or derived fromanother signal, such as a data signal or another clock. This type of clock circuit is important in
many communications or audio video applications to keep data synchronized. In a digitalFPGA-based system, this function often uses external mixed-signal ICs, which add additionalcost, power, and complexity to the system. This application note and reference design providea digital phase-locked loop (DPLL) solution that utilizes spare resources in a Virtex™-4 FPGAand requires minimal external components. The performance of the DPLL is superior to mostintegrated mixed-signal solutions. The DPLL design can be used in many different applications,including jitter reduction PLLs, clock multiplier PLLs, clock recovery PLLs, and clockgenerators.
You Might Like
Recommended ContentMore
Open source project More
Popular Components
Searched by Users
Just Take a LookMore
Trending Downloads
Trending ArticlesMore