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Optimization of digital system design based on FPGA/CPLD

  • 2013-07-01
  • 147.73KB
  • Points it Requires : 2

Abstract: This paper discusses the optimization of digital system design based on FPGA/CPLD, including area optimization, speed optimization and their relationship. Two methods of area optimization are given through examples: resource sharing method and serialization method in circuit structure. Three design principles of speed optimization are proposed: pipeline design method, register balancing method and critical path method. [Author Abstract]

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