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The algorithm for determining the true form in the VHDL synthesis system HLS/BIT

  • 2013-07-01
  • 125.29KB
  • Points it Requires : 2

Abstract: In the HDL synthesis system of EDA design tools, high-level synthesis, RTL-level synthesis and logic-level synthesis often need to make a true-for-all judgment on logic functions. This paper presents an efficient true-for-all judgment algorithm, which uses cofactors, Shannon expansions and single-sided functions to make a fast and effective recursive judgment on multidimensional arrays of logic functions. The algorithm has been applied in the self-developed VHDL synthesis system HLS/BIT.

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