Design of frequency divider based on FPGA and its implementation in VHDL

This article describes the use of VHDL to design a frequency divider on FPGA/CPLD using examples, including even frequency division, odd frequency division with non-50% duty cycle and 50% duty cycle, half-integer (N+0.5) frequency division, decimal frequency division, fractional frequency division, and integral frequency division. All implementations can be synthesized through Synplify Pro or the FPGA manufacturer\'s synthesizer to form a usable circuit and verified on ModelSim. Overview..................................................................................................................1 Counters........................................................................................................................1 Normal Counters.........................................................................................................1 Johnson Counters.........................................................................................................3 Frequency Dividers..................................................................................................................4 Even Frequency Dividers..................................................................................................4 Odd Frequency Dividers..................................................................................................6 Half-Integer Frequency Dividers..................................................................................9 Fractional Frequency Dividers........................................................................................11 Fractional Frequency Dividers........................................................................................15 Integral Frequency Dividers........................................................................................18