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DDR (Double Rate) SDRAM Controller Reference Design

  • 2013-09-22
  • 24.01KB
  • Points it Requires : 2

Contents of xapp253.zip file       contains verilog source files       *top.v* is the source file for DDR SDRAM controller       *tb_top.v* is the source file for testbench       *define.v* contains variable definitions       *mt46v4m16.v* is the simulation model of 64MB DDR SDRAM from Micron*top.ucf* is the user constraint file to be specified during         Place and Route. This contains the constraints for 133MHz implementation

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