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DDS VERILOG source code (VHDL)

  • 2013-09-22
  • 4KB
  • Points it Requires : 2

`timescale 1ns/1psmodule mydds( DATA, //frequency control word WE_F, //frequency control word write enable CLKP, //clock CE, //DDS enable ACLR, //reset SINE, //positive scintillation signal output COSINE //residual scintillation signal output); input [31 : 0] DATA; input WE_F; input CLKP; input CE; input ACLR; output [15 : 0] SINE; output [15 : 0] COSINE;

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