Integrating multiple processors on a single chip to improve the overall performance of SoC has become a trend in the design of next-generation integrated circuits. How to improve the scalability of multi-processors has become the key to the design of multi-processor system chips. Based on the AMBA bus, this paper studies the design of scalable prototype chips for multi-core SoC prototype chips. The above platform is designed at the RTL level, and the prototype is verified using FPGA. The pipeline matrix multiplication is taken as an example to study the change of its speedup ratio under different workloads. The experimental results show that in the case of six processors, the speedup ratio is only 4.10 when the number of loops is 6; as the number of loops increases, the speedup ratio can reach 5.48
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