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Introduction to Verification Methodology Based on SystemVerilog Language

  • 2013-09-22
  • 453.36KB
  • Points it Requires : 1

    This article mainly introduces how to use SystemVerilog language, verification methodology and verification library to develop advanced verification environment as described in the book \"VMM for SystemVerilog\". The article is divided into four parts. The first part outlines the basic method of verifying complex SoC with SystemVerilog language. The second part mainly introduces the use of advanced verification technology for RTL verification and defines a hierarchical verification platform structure that can reuse verification units between projects. The third part will involve system-level verification, including aspects such as the interaction between SystemVerilog and SystemC. When combined with a suitable method, SystemVerilog provides all the structures and features required to build a complete RTL and system-level (ESL) verification environment. At the same time, it fully supports interaction with System C or a C-based software test environment. The fourth part discusses the verification strategy adopted by verification, VMM methodology, and the use of standard libraries defined in \"VMM for SystemVerilog\" to support methodology. These libraries involve the basic methods discussed in the article, XVC, XVC manager, software verification, etc.

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