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Design of interleaver decoder in DVB-H channel decoding chip

2013-09-22
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Since the symbol interleaving is block interleaving, a large number of storage units are required. In the design, we use two single-port RAMs with a length of 2048 and a data width of 1 bit for reading and writing to ensure that the deinterleaved output data can be processed continuously. When the left RAM area is writing, the right RAM area is reading; and vice versa. This ensures that data can be processed continuously. The main function of the address generation module in Figure 5 is to generate read addresses and write addresses. The read and write addresses are sent to the address switching module respectively. Under the control of the read and write control lines, when one of the left RAM area and the right RAM area is in the read data state, the other is in the write data state.

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