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Hardware Implementation Based on H.264 Inverse Quantization IP

  • 2013-09-22
  • 160.35KB
  • Points it Requires : 2

This paper proposes the optimized structure and hardware implementation of the inverse quantization IP based on H.264. It can process the inverse quantization of various 4×4 blocks according to the standard. The IP can be embedded in the encoder and can also be used in the decoder. It can be used as a module in ASIC design and is also suitable for the hardware part of SOC platform design. Under the SMIC 0.18um process, the comprehensive results of Synopsys DC reached a frequency of 140MHZ, a throughput of 560 Mpixels/s, and an area of ​​46050um2, which fully meets the various grades in the standard.

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